A logic option that increases the propagation delay from a vertical pin to the interior of the device when the vertical pin is using the FastRow^™ Interconnect option to route the fan-outs of an input or bidirectional pin. Both the pin and its fan-out(s) must be assigned to the same Fast Region. The FastRow Interconnect and FastRow Interconnect Delay options are ignored if they are applied to anything other than a column (vertical) pin that is implemented as an input or bidirectional pin.

This option is available for APEX^™ II devices.