A logic option that directs the Compiler to duplicate the source node and specifies the destination node to which the source node fans out during netlist optimization.

This option is useful for removing nodes with high fan-out from the critical path in a design. For example, if a node fans out to two opposite locations in a design, the node can create a bottleneck because it wants to be close to each of its fan-outs, but cannot be in two places at the same time. By duplicating the source node you allow it to be close to the first node, and the duplicate can be close to the second node, thereby reducing the length of the critical path and increasing the speed of the circuit.

If you assign the Manual Logic Duplication logic option to a node, such as

then, the resulting node appears as

You can specify this option in the Assignment Organizer dialog box or the Assignment Editor. You can also perform manual logic duplication using the Assign Manual Logic Duplication command (right button pop-up menu) in the Equations window in the Floorplan Editor.

This option is ignored if it is applied to anything other than a logic element or a register. This option is available for Cyclone^™, Stratix^™, and Stratix^™ GX devices.