A logic option that specifies the interval of arrival between the DQ data signals and DQS signal during data transfer between a Stratix™ device and an external RAM that uses double data rate (DDR).
You can select one of the following settings:
| Phase of 90 degrees | The Compiler makes a phase shift of 90 degrees between the DQ data signals and DQS signal. |
| Phase of 72 degrees | The Compiler makes a phase shift of 72 degrees between the DQ data signals and DQS signal. |
This option is ignored if it is applied to anything other than pins intended for use with the dedicated DDR SDRAM interface. This option is available for Stratix and Stratix™ GX devices.
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