A logic option that implements an output register in an I/O cell that has a fast, direct connection to an I/O pin. Turning on the Fast Output Register option can help maximize timing performance, for example, by permitting fast clock-to-output times.

This option is ignored if it is applied to anything other than a register or an output or bidirectional pin fed by a register. This option is available for All Altera^® devices supported by the Quartus^® II software except FLEX^® 6000, MAX^® 3000, MAX 7000AE, and MAX 7000B devices.