A logic option that decreases the propagation delay from the interior of the device to the data input of the output register implemented in an I/O cell. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.
This option is available for APEX™ 20K, APEX 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, Stratix™, and Stratix™ GX devices.
You can select one of the following options:
| On | Decreases the propagation delay from the interior of the device to the data input of the I/O output register. This is the default setting. |
| Off | Increases the propagation delay from the interior of the device to the data input of the I/O output register. |
This option is ignored if it is applied to anything other an output or bidirectional pin that is associated with an output register implemented in an I/O cell.
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