A logic option assignment that allows you to insert one or more logic cells between two nodes without changing the design files. The inserted logic cell(s) act as a simple buffer and do not alter the functionality of the design. This option is useful for increasing the delay on a data path by inserting logic cell buffers to correct clock hold and for relieving routing congestion.

If you use this logic option as a single point assignment, the logic cell(s) are inserted after the assigned node. The output of the assigned node then drives the newly inserted logic cell(s), and the logic cell(s) drive the fan-outs of the node.

If you use this logic option as a point-to-point assignment between a source and destination node, you must specify the output node that drives the assigned node in the Fed by box. The logic cell(s) are inserted between the assigned node and the output node that feeds it. The output node then feeds the newly inserted logic cell(s), and the logic cells feed the assigned node.

The Compiler ignores this assignment is if it is assigned to anything other than a node. This option is available for All Altera^® devices supported by the Quartus^® II software except MAX^® 3000, MAX 7000AE, and MAX 7000B devices.

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