A logic option that implements an output enable register in an I/O cell with a fast, direct connection to an I/O pin. Turning on the Fast Output Enable Register option can help maximize timing performance, for example, by permitting fast clock-to-output enable times.

This option is ignored if it is applied to anything other than a register or an output or bidirectional pin that has a tri-state buffer controlled by a register. This option is available for APEX^™ II, Cyclone^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.