A logic option that specifies a PLL output pin for delay compensation in ZERO_DELAY_BUFFER and EXTERNAL_FEEDBACK modes. The pin must be fed by the extclk output port of the PLL. The other output pins fed by this PLL generally are not delay compensated, especially if they have different I/O standards.

This option is ignored if it is applied to anything other than a PLL output pin connected to the extclk output port of the PLL. This option is available for Stratix^™ and Stratix^™ GX devices only.