A logic option that specifies that the fan-out(s) of an input pin connected to logic elements, or the fan-out(s) of a logic element connected to output pin(s), should be fed via shared local interconnect lines. If the Local Routing Source assignment is turned on for a pin, local routing occurs only for the cells placed in adjacent LABs to which local routing is possible. If the Local Routing Source assignment is turned on for a logic element, local routing occurs only for the output pins that are adjacent to the LAB containing the logic element. Altera^® recommends that you make an explicit location assignment to the cells (input, output, logic element) to guarantee they are placed in a suitable location for local routing. You can connect logic on a speed-critical path using local routing to maximize the project performance.

This option is ignored if it is assigned to anything other than an input pin. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, and FLEX^® 6000 devices.