A logic option that duplicates a register that feeds to the output enable port of an I/O cell. Turning on this option can help maximize timing performance, for example, by permitting fast clock-to-output times.

This option is ignored if it is applied to anything other than an output enable register that feeds to the output enable port of an I/O cell. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, and ARM^®-based Excalibur^™ devices.