A logic option that decreases the propagation delay from an input pin to the data input of the input register implemented in the I/O cell associated with the pin. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.
This option is available for APEX™ 20K, APEX 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, Cyclone™, MAX® 7000B, Mercury™, Stratix™, and Stratix™ GX devices.
You can select one of the following options:
| On | Decreases the propagation delay from the input pin to the data input of the input I/O register. This is the default setting if the design does not use a PLL. |
| Off | Increases the propagation delay from the input pin to the data input of the input I/O register. This is the default setting if the design uses a PLL. |
This option is ignored if it is applied to anything other than an input or bidirectional pin.
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