A logic option that specifies whether a clock enable signal in an I/O cell should be driven by the peripheral bus or the single-pin path. The Single-Pin setting drives the clock enable signal with the local interconnect shared by the I/O cell and the adjacent LAB. The Peripheral setting drives the clock enable signal with a peripheral control bus.

This option is ignored if it is assigned to anything other than a logic function assigned to an I/O cell or the signal that drives the clock enable of the I/O cell. This option is available for ACEX^® 1K, APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, and FLEX 10KE devices.