A logic option that specifies whether an I/O element in a lower-level design entity can be temporarily mapped to a logic element and not to a pin during compilation. The virtual pin is then implemented as a register. This option should be specified only for I/O elements that become nodes when imported to the top-level design.

This option is useful when compiling a LogicLock^™ module with more pins than the current device allows. Turning on this option provides timing analysis that can more closely match the performance of the LogicLock module when it is integrated into the top-level design.

This option is ignored if it is applied to anything other than an input pin or an output pin. The Compiler ignores assignments to bidirectional pins, tri-state pins, or registered I/O elements. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.

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