A logic option that decreases the propagation delay from an input or bidirectional pin to logic and embedded cells within the device. This is an advanced option that should be used only after you have compiled a project, checked the I/O timing, and determined that the timing is unsatisfactory. For detailed information on how to use this option, refer to the data sheet for the device family.
For ACEX® 1K, APEX™ 20K, FLEX® 6000, and FLEX 10KE designs, you can turn this option on or off. For APEX 20KC, APEX 20KE, APEX™ II, ARM®-based Excalibur™, Mercury™, Stratix™, and Stratix™ GX designs, you can choose any of the following settings:
| Small | Implements a small decrease to the input delay. Creates more propagation delay from the pin to the internal cells than is allowed by the Medium setting. |
| Medium | Implements a medium decrease to the input delay. Creates more propagation delay from the pin to the internal cells than is allowed by the Large setting. |
| Large | Implements a large decrease to the input delay. Creates less propagation delay from the pin to the internal cells than is allowed by the Compiler's internal default setting. |
| On | Creates no extra input delay and yields the least propagation delay from the pin to the internal cells. This is the default setting. |
| Off | Creates the maximum propagation delay from the pin to the internal cells. This setting produces the same result as the Small setting. |
This option is ignored if it is applied to anything other than an input or bidirectional pin. This option is available for All Altera® devices supported by the Quartus® II software except MAX® 3000, MAX 7000AE, and MAX 7000B devices.
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |