A logic option that implements an input register in an I/O cell that has a fast, direct connection from an I/O pin. Turning on the Fast Input Register option can help maximize timing performance, for example, by permitting fast setup times.

This option is ignored if it is applied to anything other than a register or an input or bidirectional pin that feeds a register. This option is available for All Altera^® devices supported by the Quartus^® II software except FLEX^® 6000 and MAX^® 3000 devices.