| File Type |
Extension |
| AHDL Include File |
.inc |
| Block Design File |
.bdf |
| Block Symbol File |
.bsf |
| Chain Description File |
.cdf |
| Comma-Separated Value File |
.csv |
| Compiler Settings File |
.csf |
| Conversion Setup File |
.cof |
| Cross-Reference File |
.xrf |
| database files |
.cdb, .hdb, .rdb, .tdb |
| EDIF Input File |
.edf, .edif |
| Executable and Linkable Format File |
.elf |
| Entity Settings File |
.esf |
| Graphic Design File |
.gdf |
| HardCopy™ files |
.datasheet, .sdo, .tcl, .vo |
| Hexadecimal (Intel-Format) File |
.hex |
| Hexadecimal (Intel-Format) Output File |
.hexout |
| HTML-Format Report File |
.htm |
| IBIS Output File |
.ibs |
| In System Configuration File |
.isc |
| Jam™ Byte-Code File |
.jbc |
| Jam File |
.jam |
| Library Mapping File |
.lmf |
| License File |
license.dat |
| Master Port High-Level Command File |
.dat |
| Memory Initialization File |
.mif |
| Memory Map File |
.map |
| Motorola S-Record File |
.srec |
| PartMiner edaXML-Format File |
.xml |
| Pin-Out File |
.pin |
| Power Input File |
.pwf |
| programmable logic Partial SRAM Object File |
.psof |
| Programmer Object File |
.pof |
| programming files |
.cdf, .cof |
| Project Settings File |
.psf |
| Project Configuration File |
.quartus |
| Quartus® Workspace File |
.qws |
| Quartus II Archive File |
.qar |
| Quartus II Archive Log File |
.qarlog |
| RAM Initialization File |
.rif |
| Raw Binary File |
.rbf |
| Routing Constraints File |
.rcf |
| Serial Vector Format File |
.svf |
| settings & configuration files |
.csf, .esf, .fsf, .psf, .ssf, .quartus, .qws |
| SignalTap® II File |
.stp |
| Simulator Settings File |
.ssf |
| Slave Binary Image File |
.sbi |
| Software Build Settings File |
.fsf |
| SRAM Object File |
.sof |
| Standard Delay Format Output File |
.sdo |
| Symbol File |
.sym |
| System Build Descriptor File |
.sbd |
| Tab-Separated Value File |
.txt |
| Tabular Text File |
.ttf |
| Tcl Script File |
.tcl |
| Text Design File |
.tdf |
| Text-Format Report File |
.rpt |
| Timing Analysis Output File |
.tao |
| Token File |
ted.tok |
| uPCore Transaction Model Input File |
.mbus_in |
| uPCore Transaction Model Output File |
.mbus_out |
| uPCore Transaction Model Slave Configuration File |
.cfg.sbus_in |
| uPCore Transaction Model Slave Input File |
.sbus_in |
| uPCore Transaction Model Slave Output File |
.sbus_out |
| Vector File |
.vec |
| Vector Table Output File |
.tbl |
| vector source files |
.pwf, .tbl, .vwf, .vec |
| Vector Waveform File |
.vwf |
| Verilog Design File |
.v, .vqm, .verilog |
| Verilog Output File |
.vo |
| Verilog Quartus Mapping File |
.vqm |
| Verilog Test Bench File |
.vt |
| Verilog Value Change Dump File |
.vcd |
| VHDL Design File |
.vhd, .vhdl |
| VHDL Output File |
.vho |
| VHDL Test Bench File |
.vht |
| XML files |
.cof, .stp, .xml |
| waveform files |
.stp, .tbl, .vec, .vwf |
