An ASCII text file (with the extension .sbus_out) generated by the Simulator when you simulate an ARM^®-based Excalibur^™ design that contains an embedded processor core. This file describes the bus transactions between the PLD and the embedded processor core during simulation, via the Stripe Slave-Port.

To generate an uPCore Transaction Model Slave Output File, you must first specify an appropriate uPCore Transaction Model Input File (.mbus_in). You can also optionally create an uPCore Transaction Model Slave Configuration File (.cfg.sbus_in) and the corresponding uPCore Transaction Model Slave Input Files (.sbus_in) for use during simulation. The Simulator uses the uPCore Transaction Model Slave Configuration File and uPCore Transaction Model Slave Input Files to simulate the bus transactions (tat is, read and write operations) that occur between the PLD and the embedded processor core via the Stripe Slave-Port.

If no uPCore Transaction Model Slave Configuration File and uPCore Transaction Model Slave Input Files exist in the project directory, the bus transactions that occur on the Stripe Slave-Port still are written to the uPCore Transaction Model Slave Output File. However, any return information from the memory banks in the stripe is set to zero.