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LogicLock^™ regions are flexible, reusable floorplanning constraints that increase your ability to guide logic placement on the target device. Together with incremental synthesis, LogicLock regions support team-oriented, modular design by enabling you to optimize logic blocks individually, then import them and their placement constraints into a larger design.

A LogicLock region is a user-defined rectangular region. When you assign nodes or entities to a LogicLock region, you direct the Fitter to place those nodes or entities inside the region during fitting. There are four types of LogicLock regions:

• fixed size, locked location
• fixed size, floating location
• auto-size, floating location
• soft regions (allows the Fitter to place the design elements in the region outside region boundaries)

The Quartus^® II software determines an optimal size and location for auto-size and floating regions during compilation. If you are satisfied with the size or location chosen, you can back-annotate the size or location for reuse on subsequent compilations.

You can create LogicLock regions in the Timing Closure floorplan or the Current Assignments Floorplan, the LogicLock Regions window, or the Project Navigator. You can assign nodes and entities to LogicLock regions by using the Assignment Organizer dialog box or by dragging and dropping them from the Node Finder or from the Compilation Hierarchies folder in the Project Navigator. LogicLock regions are displayed in the Floorplan Editor. You can also create and manipulate LogicLock regions by using Quartus II Tcl API functions.

In the LogicLock Region Properties dialog box, you can specify properties, add path-based assignments, and specify Fitter priority for path-based and wildcard assignments for the selected LogicLock region(s).

You can flip regions horizontally on a device in the LogicLock Region Properties dialog box and the Floorplan Editor.

LogicLock regions can be nested hierarchically. Making one LogicLock region the child of another LogicLock region places the child region inside its parent region and specifies that the child's location is relative to its parent's location. When you move a parent region, its child regions maintain their placement relative to the parent region. You can only create parent and child LogicLock regions in the LogicLock Regions window.

LogicLock back-annotation allows you to back-annotate all nodes in a LogicLock region relative to the edges of the region. When you move a back-annotated region, its member nodes maintain their relative placement in the new location. The Quartus II software does not support back-annotation of soft regions.

LogicLock region assignments can be exported in an Entity Settings File (.esf) for reuse in other designs. This feature enhances support for modular design, since it allows you to design, test, and optimize entities individually, and preserve their placement and performance when you import them into a larger project.

You can create a LogicLock region without assigning nodes or entities to it. It remains in the project and is displayed in the Floorplan Editor and the LogicLock Regions window until you delete it, regardless of whether any nodes are currently assigned to it. You can also show LogicLock Region connectivity.

LogicLock regions are currently supported for APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.

	More information is available on LogicLock regions on the Altera® web site.

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