A LogicLock^™ region is a type of placement constraint. You can define any arbitrary rectangular region of physical resources on the target device as a LogicLock region. Assigning nodes or entities to a LogicLock region directs the Compiler to place those nodes or entities inside the region during fitting.

There are four types of LogicLock regions:

• fixed size, locked location
• fixed size, floating location
• auto-size, floating location
• soft regions (direct the Fitter to place the design elements in the region as close together and in the best location possible)

The Quartus^® II software determines an optimal size and location for auto-size and floating regions during compilation. If you are satisfied with the size or location chosen, you can back-annotate the size or location for reuse on subsequent compilations.

LogicLock back-annotation allows you to back-annotate all nodes in a LogicLock region. Nodes back-annotated with LogicLock back-annotation are locked relative to the edges of the region. If you move a back-annotated region, its member nodes maintain their relative placement in the new location.

LogicLock regions can be nested hierarchically. If you move a parent region, child regions maintain their placement relative to their parent region.

LogicLock assignments can be exported in an Entity Settings File (.esf) for reuse in other designs.

You can create a LogicLock region without assigning nodes or entities to it. It remains in the project and is visible in the Floorplan Editor and the LogicLock Regions window until you delete it, regardless of whether any nodes are currently assigned to it.

LogicLock regions are currently supported for APEX^™ 20K, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.

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