The saving of an entity's intermediate synthesis results for reuse in other projects.

When you compile with the Incremental Synthesis option on the Synthesis page in the Settings dialog box (Assignments menu) turned on, the Quartus^® II software saves an ATOM-based netlist for the current compilation focus to a Verilog Quartus^® Mapping File (.vqm).

You can use the VQM File as the entity's source file when you instantiate the entity in a new project. Instantiating an entity from a VQM file ensures that node names within the entity remain the same, regardless of other entities in the design. For this reason, Altera^® recommends that you use incremental synthesis when you export node-level assignments such as LogicLock^™ back-annotation from one project and import them into another project. By using incremental synthesis to generate a VQM File for an entity when you export its assignments, and by instantiating the entity from the VQM File in the project where you import the assignments, you ensure that the node names synthesized in the new project correspond to the node names in the imported assignments.

If you are already compiling from EDIF Input Files (.edf) or VQM Files, which are ATOM-based netlists, you do not need to perform incremental synthesis with the Quartus II software.

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