See Also

You can use the Floorplan Editor to assign physical device resources or to view Compiler partitioning, fitting, and timing results.

In the Floorplan Editor, you can assign logic to a device, a row or column within a device, MegaLAB^™ structure, LAB, pin, or logic cell (including embedded and I/O cells). In addition, you can use the Regions window to assign logic to a specific section within a device.

After you compile a project, you can use the Floorplan Editor to view the Compiler's logic placement. You can display the non-editable (read-only) Last Compilation floorplan or the editable Current Assignments floorplan. After compiling a design, you can back-annotate the results of a compilation to preserve the resource assignments made during the last compilation. You can also use the editable Timing Closure floorplan to view logic placement made by the Fitter and/or by user assignments, make LogicLock^™ region assignments, and view critical path information, physical timing estimates, and routing congestion.

If you compile a design that is targeted for an ARM^®-based Excalibur^™ device, you can also view the Excalibur embedded processor stripe in the Floorplan Editor. The stripe is located between the logic cells and pins, and contains interfaces to the embedded logic for the microprocessor, as well as to the dual-port RAM.

Resource usage in the Floorplan Editor is color-coded. The Color Legend window displays a key for interpreting the color code. Different colors represent different resources, such as unassigned and assigned pins and logic cells; unrouted items; and MegaLAB structures, columns, and row FastTrack^® fan-outs. You can display floorplan information in the following ways:

• The Package Top and Package Bottom views show all pins on a device package and their function.
• The Interior MegaLABs, Interior LABs, and Interior Cells views show the interior structure of the device, including all MegaLAB structures, LABs, logic cells, and pins within a device.
• The Regions window shows relevant regions of the device: chip, anywhere on device, MegaLAB row, Excalibur region, MegaLAB column, MegaLAB row halves, MegaLAB column halves, section, and fast regions.
• The Selected Signal window allows you to view the name and location of selected assignments and the type of selected signals.
• The Field View command, which is available only when using the Timing Closure floorplan, allows you to view histograms indicating the amount of user assigned, Fitter placed, and unassigned logic per structure in the device.
• You can also view physical timing estimates in the Field view, which provides a graphical representation of the relative routing delay estimate to a selected structure in the device.

To edit assignments in the Floorplan Editor, you can click an assignment and drag it to a new location, such as a LAB or MegaLAB assignment bin. Assigning a cell to a MegaLAB bin, for example, allows the Compiler to select the most efficient location within a MegaLAB structure. While dragging a structure in the Floorplan Editor, you can use rubberbanding to display a visual representation of the number of routing resources affected by the move.

You can view the critical paths or routing congestion in a design, view routing delay information for paths, and view connection counts to specific nodes. You can also view the node fan-out and node fan-in for specific structures, or view the paths between specific nodes. You can use this information to identify critical paths and/or to assign to LogicLock regions when using the Timing Closure floorplan.

You can also select pins or logic cells in the Floorplan Editor and view them in the Synplify HDL Analyst.

The Floorplan Editor provides many other useful features. For example, you can zoom in and out to various magnifications, so that you can see all of a device or a detailed portion of it. You can copy, cut, paste, and delete one or more selected assignments, and search for an assignment by its pin or logic cell number or its node name.

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