See Also

The Compiler is a highly automated design processor that transforms design files in a design into output files for device programming, simulation, and timing analysis, and then optionally performs a timing analysis on the design.

You can use the Compiler to process EDIF Input Files (.edf), Block Design Files (.bdf), Verilog Design Files (.v), VHDL Design Files (.vhd), or Text Design Files (.tdf) created by the Quartus^® II Block Editor or Text Editor, or other industry-standard CAE tools.

When you start the Compiler, it begins a series of processes that ultimately creates one or more programming files. While the Compiler can compile a project with minimal assistance, it also allows you to customize processing for a particular design. The Compiler gives you the freedom to experiment with a variety of processing options. You can also configure the Compiler to generate a variety of output files, including VHDL Output Files (.vho), Verilog Output Files (.vo), and Standard Delay Format Output Files (.sdo), for use with simulation tools from other EDA vendors.

The Database Builder module of the Compiler first checks the design files and the overall design for errors, and then builds a single design database that integrates all the design files in a design hierarchy. Each subsequent Compiler module—the Logic Synthesizer, Fitter, and Assembler—updates the database until it contains the fully minimized, fitted design, which is used to create one or more files for device programming.

The Delay Annotator module of the Compiler computes delays for the given design and device and annotates them on the netlist for subsequent use by timing-driven compilation, the Simulator, or the Timing Analyzer. The Timing Analyzer allows you to analyze the performance of a design after it has been synthesized by the Compiler. For more information about the Timing Analyzer, go to Overview: Using the Timing Analyzer.

The Compiler generates the Report window, Text-Format Report File (.rpt) and HTML-Format Report File (.htm) for the compilation, which displays information about the current Compiler settings and shows how the design is implemented in a device. The Messages window and the Messages section of the Report window or Report File display any messages the Compiler generates, thus allowing you to interactively locate and correct design file errors as they are detected during design compilation. The Status window and the Processing Time section of the Report window and Report File record the time spent processing in the different Compiler modules during design compilation.

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