|
|
The Summary section in the Compilation Report displays the following summary information about the compilation:
| Heading | Description | Value |
|---|---|---|
| Processing Status | Shows the status of the design processing and fitting into the device. | Fitting Successful | Fitting Unsuccessful |
| Timing requirements/analysis status | Shows the status of specified timing requirements, if any. | Timing not analyzed | No requirements | Requirements met | Requirements not met |
| Chip name | Shows the name specified for the chip, inherited from the current Compilation focus for the design, as specified in the General page of the Settings dialog box (Assignments menu). | <chip name> |
| Device for compilation | Shows the name of the current device that you specified in the Available Devices list in the Device page of the Settings dialog box (Assignments menu). The Compiler can also select the appropriate device in the Available Devices list when you select Auto device selected by the Compiler from the 'Available devices' list. | <device name> |
| Total logic elements | Shows the total number of logic elements used, displayed as both a ratio and a percentage. This information does not appear if you specify a MAX® 3000 or MAX 7000 device for compilation. |
<number> / <total available> (<percent used> %) |
| Total macrocells | Shows the total number of macrocells used, displayed as both a ratio and a percentage. This information appears only if you specify a MAX 3000 or MAX 7000 device for compilation. |
<number> / <total available> (<percent used> %) |
| Total pins | Shows the total number of pins used, displayed as both a ratio and a percentage. | <number> / <total available> (<percent used> %) |
| Total ESB bits |
Shows the total number of Embedded System Block (ESB) bits used, displayed as both a ratio and a percentage. The <number> variable represents the total number of memory bits plus product term bits (where 1 product term cell equals 2,048 bits/16 outputs or 128 bits). The <total available> variable represents the total number of available ESB bits (or the number of ESBs x 2,048 bits). This information appears only if you specified an APEX™ 20K, APEX 20KC, APEX 20KE, APEX™ II, or ARM®-based Excalibur™ device for compilation. |
<number> / <total available> (<percent used> %) |
| Total EAB bits |
Shows the total number of Embedded Array Block (EAB) bits used, displayed as both a ratio and a percentage. The <number> variable represents the total number of memory bits used. The <total available> variable represents the total number of available EAB bits (or the number of EABs x 4,096 bits). This information appears only if you specified an ACEX® 1K or FLEX 10KE device for compilation. |
<number> / <total available> (<percent used> %) |
| Total memory bits | Shows the total number of memory bits used, displayed as both a ratio and a percentage. The total amount of memory bits represents the total number of memory bits available in the M512 and M4K memory blocks and mega RAMs in Stratix™ and Stratix™ GX devices, or the total number of memory bits available in the M4K memory blocks in a Cyclone™ device | <number> / <total available> (<percent used> %) |
| DSP block 9-bit elements | Shows the total number of DSP blocks 9-bit elements used, displayed as both a ratio and a percentage. DSP block 9-bit elements make up the DSP blocks in a Stratix or Stratix GX device. | <number> / <total available> (<percent used> %) |
| PLLs | Shows the total number of PLLs used, displayed as both a ratio and a percentage. This information appears only if you specified a Cyclone, Stratix, or Stratix GX device for compilation. | <number> / <total available> (<percent used> %) |
| Device for timing analysis | Shows the device used for performing a timing analysis. | <device name>) |
The following example shows the Summary section of the Compilation Report for a sample design:
The Summary section of the Simulation Report displays the following summary information about the simulation:
| Option | Value |
|---|---|
| Simulation Start Time | Shows the start time for the simulation. |
| Simulation End Time |
Shows the end time for the simulation. You can specify an end time under Simulation period in the Time/Vectors page (Settings dialog box) by selecting Run simulation until all vector stimuli are used, or by selecting End simulation at and typing a time in the box. |
| Simulation Coverage | Shows the ratio of nodes actually simulated compared to the number of nodes in the Vector Waveform File (.vwf) or Vector File (.vec), expressed as a percentage. This value is displayed only if you turn on Simulation coverage reporting in the Options page (Settings dialog box) before performing the simulation. |
| Number of transitions | Shows the number of transitions that occurred during a timing simulation. |
| Internal Power | Shows the estimated amount of internal power consumed in milliWatts (mW) by entities in the current APEX 20KE, APEX 20KC, ARM-based Excalibur, or Mercury™ design during the simulation. This value is displayed only if you turn on Estimate power consumption in the Options page (Settings dialog box) or specify a Power Input File (.pwf) in the Source of vector stimuli box in the Time/Vectors page (Settings dialog box) before performing the simulation. |
| I/O Power | Shows the estimated amount of power consumed in mW by I/O pins in the current APEX 20KE, APEX 20KC, or Mercury design during the simulation. This value is displayed only if you turn on Estimate power consumption in the Options page (Settings dialog box) or specify a Power Input File in the Source of vector stimuli box in the Time/Vectors page (Settings dialog box) before performing the simulation. |
| Total Power | Shows the total estimated amount of power consumed in mW by the current APEX 20KE, APEX 20KC, or Mercury design during the simulation. This value is displayed only if you turn on Estimate power consumption in the Options page (Settings dialog box) or specify a Power Input File in the Source of vector stimuli box in the Time/Vectors page (Settings dialog box) before performing the simulation. |
The following example shows the Summary section of the Simulation Report generated after simulating a sample design:
|
- PLDWorld - |
|
|
| Created by chm2web html help conversion utility. |