A synchronous dual-port memory block, with registered inputs and optionally registered outputs, available in Stratix^™ and Stratix^™ GX devices. The M512 block is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block is a 32 × 18 RAM block and contains 576 programmable bits, including parity bits. The M512 block can be configured as dual- and single-port RAM, FIFO buffers, and ROM, and you can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to pre-load the memory contents when the M512 memory block is configured as a RAM or ROM.

When implementing memory in Stratix and Stratix GX devices, the M512 memory block can be configured in any of the following sizes:

Operation Mode	M512 Memory Block Size
Single-port and ROM	32 × 18 64 × 9 128 × 4 256 × 2 512 × 1
Dual-port	Write × 1 / Read × N W × 2 / R × N W × 4 / R × 4 W × 18 / R × 18 W × 4 / R × 16 W × 16 / R × 4 W × N / R × 1 W × N / R × 2 W × 9 / R × 9 N = 1, 2, 4, 8, or 16

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