The phase-locked loop (PLL) block is a feedback control system that automatically adjusts the phase of a locally generated signal to match the phase of an input signal. PLLs operate by producing an oscillator frequency to match the frequency of an input signal. In this locked condition, any slight change in the input signal first appears as a change in phase between the input signal and the oscillator frequency. This phase shift then acts as an error signal to change the frequency of the local PLL oscillator to match the input signal. The locking-onto-a-phase relationship between the input signal and the local oscillator accounts for the name phase-locked loop. PLLs are often used in high-speed communication applications.
The following types of specialized PLLs are supported by Altera® devices:
| PLL Type | Device Family Support |
|---|---|
| ClockLock® PLL | ACEX® 1K, APEX™ 20K, APEX™ II, ARM®-based Excalibur™, FLEX 10KE, and Mercury™ device families |
| enhanced PLL | Stratix™ and Stratix™ GX devices only |
| fast PLL | Stratix and Stratix GX devices only |
| GXB receiver PLL and GXB transmitter PLL | Stratix GX devices only |
| HSDI PLL | Mercury devices only |
| LVDS PLL | APEX 20KC, APEX 20KE, APEX II, and ARM-based Excalibur device families |
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