See Also

Lists the options and their settings for the current project. The following options are available:

Allow XOR Gate Usage
Auto Carry Chains
Auto Cascade Chains
Auto Delay Chains
Auto DSP Block Replacement
Auto Global Clock
Auto Global Memory Control Signals
Auto Global Output Enable
Auto Global Register Control Signals
Auto Implement in ROM
Auto Merge PLLs
Auto Open-Drain Pins
Auto Packed Registers
Auto Parallel Expanders
Auto RAM Replacement
Auto Shift Register Replacement
Auto Turbo Bit^™
Carry Chain Length
Cascade Chain Length
DSP Block Balancing
Enable Bus-Hold Circuitry
Ignore CARRY Buffers
Ignore CASCADE Buffers
Ignore GLOBAL Buffers
Ignore LCELL Buffers
Ignore ROW GLOBAL Buffers
Ignore SOFT Buffers
Limit AHDL Integers to 32 Bits
Logic Cell Insertion - I/Os Fed by Carry or Cascade Chains
Logic Cell Insertion - Individual Logic Cells
NOT Gate Push-Back
Optimization Technique
Parallel Expander Chain Length
PCI I/O
Power-Up Don't Care
Remove Duplicate Logic
Remove Duplicate Registers
Remove Redundant Logic Cells
Slow Slew Rate
State Machine Processing
Technology Mapper
Turbo Bit
Weak Pull-Up Resistor

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