A logic option that allows the Compiler to choose signals that feed the most control signal inputs to registers (excluding clock signals) as global signals made available throughout the device on the global routing paths. Depending on the device family, these control signals can include asynchronous clear, synchronous clear, asynchronous load, synchronous load, preset, clock enable, and output enable signals.

This option is ignored if it is assigned to anything other than a design entity. If you want to prevent the Compiler from automatically selecting a particular signal as a global register control signal, set the Global Signal logic option to Off for that signal. This option is available for all Altera^® devices supported by the Quartus^® II software.

The following control signals are available for each device family:

	ACEX® 1K, FLEX 10KE	APEX™ 20K, APEX™ II, ARM®-based Excalibur™	FLEX® 6000	MAX® 3000, MAX 7000	Mercury™	Stratix™, Stratix™ GX
asynchronous clear (clear)
synchronous clear		(LE only)			(LE only)
asynchronous load	(LE only)
synchronous load					(LE only)
asynchronous preset (preset)	(LE only)
clock enable	(I/O) cell register only	(I/O) cell register only

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