A logic option that allows the Compiler to use the XOR gate that exists in a macrocell (that is, in an embedded cell within an Embedded System Block (ESB) that is set to use Product Term mode).

This option is ignored if it is assigned to anything other than a design entity. The Allow XOR Gate Usage option is also ignored if you select LUT or ROM as the setting for the Technology Mapper option. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, MAX^® 3000, MAX 7000AE, and MAX 7000B devices.