Glossary

Remove Duplicate Logic logic option


A logic option that removes logic if it is identical to other logic in the design. If two functions generate the same logic, the second one is deleted and the first one is made to fan-out to the second one's destinations. Also, if the deleted logic function has different logic option assignments, they are ignored. Turning this option off prevents the Compiler from removing duplicate logic that you have used deliberately. However, if a function's output feeds an LCELL buffer, the Compiler always treats it as a unique signal and the Remove Duplicate Logic option does not apply. This option also performs the function of the Remove Duplicate Registers option, that is, if this option is on, it will removed all duplicate logic, including duplicate registers. To direct the Compiler to not remove duplicate registers in the design when this option is turned on, turn off the Remove Duplicate Registers option for those registers.

The following example shows how the Remove Duplicate Logic option can affect logic:

Before: t=a&w y=b&z z=c&d#e&f; w=c&d#e&f;
After: t=a&z y=b&z z=c&d#e&f;

This option is ignored if it is assigned to anything other than a design entity. This option is available for all Altera® devices supported by the Quartus® II software.


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