A logic option that allows the Compiler to find a set of registers and logic that can be replaced with the altsyncram or the lpm_ram_dp megafunction. Turning on this option may change the functionality of the design.
This option is useful for finding areas of the design that can be implemented more efficiently, and as a result, minimizing the area and maximizing the speed of the design.
This option is ignored if it is assigned to anything other than an entity. This option is available for All Altera® devices supported by the Quartus® II software except FLEX® 6000, MAX® 3000, MAX 7000AE, and MAX 7000B devices.
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