A logic option that allows the Fitter to chose the optimal delay chain setting from the Decrease Input Delay to Input Register, Decrease Input Delay to Internal Cells, Decrease Input Delay to Output Register, Increase Clock Enable Delay, Increase Delay to Output Enable Pin, Increase Delay to Output Pin, Increase Input Clock Enable Delay, Increase Output Clock Enable Delay, Increase Output Enable Clock Enable Delay, or Increase tzx Delay to Output Pin logic options to meet t_SU and t_CO timing requirements for all I/O elements. Turning on this option may reduce the number of t_SU violations while introducing a minimal number of t_H violations. Turning on this option does not override delay chain settings on individual nodes.

This option is useful for automatically meeting t_SU timing requirements by adjusting the delay chain setting, rather than by adjusting the timing requirements on individual pins and performing multiple compilations to get the optimal delay for the design.

This is a project-wide setting. This option is available for Cyclone^™, Stratix^™, and Stratix^™ GX devices.

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