A logic option that allows the Compiler to automatically implement pairs of logic functions in the same logic cell. This option controls how aggressively the Fitter attempts to place a pair of logic functions, one combinational and one sequential, in the same logic cell to reduce logic element count.

Use the following settings:

Off	The Fitter does not attempt to place a pair of logic functions in a single logic cell; however, logic cells specified during synthesis to perform both a combinational and a sequential function are maintained. This is the default setting for all devices that this option supports, except Cyclone™, Stratix™, and Stratix™ GX devices.
Normal	The Fitter places both a combinational and a sequential operation in a logic cell when it is expected that the placement will not affect design performance. This is the default setting for Cyclone, Stratix, and Stratix GX devices. For ACEX® 1K, FLEX 10KE, and Mercury™ devices, this setting has the same behavior as the Off setting.
Minimize Area	The Fitter aggressively combines unrelated sequential and combinational functions into a single logic cell to reduce the logic element count, even at the expense of design performance.
Minimize Area with Chains	The Fitter aggressively combines sequential and combinational functions that are part of arithmetic or register cascade chains, or that can be converted to register cascade chains. This option is available for Cyclone, Stratix, and Stratix GX devices.

If this option is set to Normal, Minimize Area, or Minimize Area with Chains, the Fitter merges the registers with I/O cells to improve I/O timing in Cyclone, Stratix, and Stratix GX devices. In Stratix and Stratix GX devices, if this option is set to B>Normal, Minimize Area, or Minimize Area with Chains, the Fitter merges the registers with DSP blocks to reduce logic cell count or to improve timing when possible.

This option is ignored if it is assigned to anything other than a design entity. If the register and the other cell being considered for placement in the same logic cell, I/O cell, or DSP block have different settings for the Auto Packed Registers option, the less aggressive of the two settings determines if the Fitter can place the combination together. This option is available for all Altera^® devices supported by the Quartus^® II software except FLEX^® 6000, MAX^® 3000, MAX 7000AE, and MAX 7000B devices.