A logic option that allows the Compiler to automatically find and merge together two compatible phase-locked loops (PLL) driven by the same clock source, reducing the total number of PLLs used in a design.

This option is useful for decreasing the total number of PLLs in a design that did not fit into the target device during compilation.

This option is ignored if it is applied to anything other than a node. This option is available for Cyclone^™, Stratix^™, and Stratix^™ GX devices.

Back to Top