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Lists information about the output pins in the device.
Information is provided as follows:
| Heading | Description | Value |
|---|---|---|
| Name | Shows the name of the pin. | <pin name> |
| Pin # | Shows the pin number. | <pin number> |
| Migration Pin # | Shows the pin number of the largest compatible migration device. This column appears only if you specify an ACEX® 1K, FLEX 10KE, or MAX® 7000 device for compilation and turn on Base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame™ device in the Migration Devices dialog box, which is available from the Device page in the Settings dialog box (Assignments menu). |
<migration pin number> |
| X coordinate | Shows the X coordinate location of the input pin. This column appears only if you specify a Cyclone™, Stratix™, or Stratix™ GX device for compilation. |
<X coordinate> |
| Y coordinate | Shows the Y coordinate location of the input pin. This column appears only if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
<Y coordinate> |
| Cell number | Shows the cell number that corresponds to the input pin. This column appears only if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
<cell number> |
| MegaLAB™ Row |
Shows the MegaLAB row number to which the pin is assigned. This column only appers if you specify an APEX™ 20K, APEX 20KC, APEX 20KE, APEX™ II, or ARM®-based Excalibur™ device for compilation. |
<MegaLAB row number> |
| MegaLAB Col. |
Shows the MegaLAB column number to which the pin is assigned. This column appears only if you specify an APEX 20K, APEX 20KC, APEX 20KE, APEX II, or ARM-based Excalibur device for compilation. |
<MegaLAB column number> |
| LAB |
Shows the LAB number to which the pin is assigned. This column appears only if you specify a MAX 3000 or MAX 7000 device for compilation. |
<LAB number> |
Row |
Shows the row to which the pin is assigned. This column appears only if you specify an ACEX 1K or FLEX 10KE device for compilation. |
<row number> |
| Col. | Shows the column number to which the pin is assigned. | <column number> |
| I/O Register | Shows whether the pin uses an I/O register to register either an input or output signal. This column does not appear if you specify an APEX II device for compilation. |
yes | no |
| Output Register | Shows whether the pin uses an output register to register an output signal. This column appears only if you specify an APEX II, Cyclone, MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
yes | no |
| Output Enable Register | Shows whether the pin uses an output enable register. This column appears only if you specify an APEX II, Cyclone, Stratix, or Stratix GX device for compilation. |
yes | no |
| Use Local Routing Output | Shows whether the pin uses a local routing resource to route out of the adjacent LAB. This column does not appear if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
yes | no |
| Power Up High | Shows, if a peripheral register exists, whether the pin powers up high. This column does not appear if you specify a MAX 3000 device for compilation. |
yes | no |
| Slow Slew Rate | Shows whether the Slow Slew Rate option is applied to the pin. | yes | no |
| Delay Chain | Shows whether the pin uses an output delay chain. This column does not appear if you specify a MAX 3000 or MAX 7000AE device for compilation. |
yes | no |
| PCI I/O Enabled | Shows whether the PCI I/O option is applied to the pin. The PCI clamp diode is turned on automatically when you turn on this option. This column does not appear if you specify a FLEX® 6000, MAX 3000, or MAX 7000 device for compilation. |
yes | no |
| Single-Pin OE | Shows whether the output enable signal is driven from the local interconnect. This column does not appear if you specify a Cyclone, MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
yes | no |
| Single-Pin CE | Shows whether the clock enable signal is driven from the local interconnect. This column does not appear if you specify a Cyclone, MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
yes | no |
| Open Drain | Shows whether the Auto Open-Drain Pins option is applied to the pin. | yes | no |
| Bus Hold |
Shows whether the Enable Bus-Hold Circuitry logic option is applied to the pin. This column appears only if you specify an APEX II, Cyclone, MAX 7000B, Mercury™, Stratix, or Stratix GX device for compilation. |
yes | no |
| I/O Standard |
Shows the I/O standard assigned to the pin. This column does not appear if you specify a FLEX 6000 device for compilation. |
1.5-V | 1.8-V | 2.5-V | 3.3-V PCI | 3.3-V PCI-X | 3.3-V PCML | AGP 1x | AGP 2x | Compact PCI | CTT | Differential HSTL | Differential SSTL-2 | GTL GTL+ | HSTL Class I, II | HSTL Class III, IV | HyperTransport™ | LVCMOS | LVDS | LVPECL | LVTTL | SSTL-2 Class I, II | SSTL-3 Class I, II | SSTL-18 Class I, II | TTL |
| Current Strength | Shows, in microamperes (mA), the strength of the current on the pin. This column appears only if you specify an APEX II, Cyclone, Mercury, Stratix, or Stratix GX device for compilation. |
<current> mA | Maximum Current | Minimum Current |
| Weak Pull Up | Shows whether the Weak Pull-Up Resistor logic option has been turned on for the pin. This column appears only if you specify an APEX II, Cyclone, MAX 7000B, Mercury, Stratix, or Stratix GX device for compilation. |
On | Off |
| Termination | Shows whether the Termination logic option is applied to the output pin. This column appears only if you specify a Cyclone, Mercury, Stratix, or Stratix GX device for compilation. |
On | Off |
The following example shows a portion of the Output Pins section generated for a sample design:
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