See Also

When you assign an entity to a LogicLock^™ region, the assignment is inherited by all lower-level entities and nodes contained in that entity. However, the assignment is not inherited by pins contained in that entity.

If you assign an entity to a LogicLock region and assign one of its sub-entities or nodes to another LogicLock region, the more specific assignment on the sub-entity or node overrides the inherited assignment. For example, if you assign entity filter to region LLR_0 and sub-entity filter|adder:my_adder to region LLR_1, the sub-entity is placed in LLR_1, and all other sub-entities and nodes in filter are placed in LLR_0.

You can prevent a node or entity from inheriting a higher-level LogicLock region assignment by turning on the Prevent Assignment to LogicLock Regions logic option for the node or entity.

If you explicitly assign a pin to a LogicLock region (for example, by selecting the pin name in the Node Finder and assigning it to the LogicLock region), the Compiler honors the assignment only if the region and all its ancestor LogicLock regions have locked locations. In this case, the Compiler attempts to place the pin inside the LogicLock region. For APEX^™ 20K, APEX^™ II, and ARM^®-based Excalibur^™ devices, the physical pins adjacent to the edges of a LogicLock region are considered to be inside the LogicLock region. For other device families, only the physical pins inside the boundaries of the LogicLock region are considered to be inside the LogicLock region.

Carry chains, cascade chains, and cliques cannot cross LogicLock region boundaries. If you assign some nodes in a carry chain, cascade chain, or clique to a parent LogicLock region and other nodes in the same chain or clique to descendant LogicLock regions along a single branch of the LogicLock region hierarchy, the Compiler places all nodes in the chain or clique inside the lowest-level region to which nodes in the chain or clique are assigned. In all other cases when nodes in the same chain or clique are assigned to different LogicLock regions, the Compiler produces an error message.

Other assignments in the Quartus^® II software take precedence over LogicLock region assignments. When a node or entity has both a LogicLock region assignment and another assignment with a higher precedence, the Fitter ignores the LogicLock region assignment and produces a warning message. Types of assignments that take precedence over LogicLock region assignments include:

• location assignments
• the Fast Input Register, Fast Output Register, and Fast Output Enable Register logic options

In addition, the Fitter may ignore LogicLock region assignments on nodes or entities that require special physical resources, such as PLLs, regional clocks, or pins with particular I/O standards.

LogicLock region assignments take precedence over the Optimize I/O cell register placement for timing option available under Timing-Driven Compilation on the Fitting page in the Settings dialog box. However, for Cyclone^™, Stratix^™, and Stratix^™ GX devices, in the case of absolutely locked LogicLock regions that extend onto pins, the Fitter attempts to honor both the LogicLock region assignment and the Optimize I/O cell register placement for timing option.

When you delete an entity or node from a LogicLock region, the Quartus II software deletes all back-annotated node locations in that region.

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