A logic option that prevents the current node or entity from being assigned to any LogicLock^™ regions. You can use this option to prevent specific sub-entities or nodes from inheriting the LogicLock region assignments on a higher-level entity.

If you turn on the Prevent Assignment to LogicLock Regions logic option for a node or entity that is explicitly assigned to a LogicLock region (that is, a node or entity that does not simply inherit its LogicLock region assignment from a higher-level entity), you must delete the node or entity from the LogicLock region before compiling the design.

Although turning on the Prevent Assignment to LogicLock Regions logic option for an entity overrides LogicLock region assignments inherited from higher-level entities, this logic option does not override explicit LogicLock region assignments on sub-entities or nodes contained in that entity. For example, if you turn on the Prevent Assignment to LogicLock Regions logic option for an entity and also assign a node contained in that entity to a LogicLock region, the Fitter attempts to place this node in the assigned LogicLock region. In general, the Fitter resolves inheritance of LogicLock region assignments by checking for the most specific assignment on each node.

This option is ignored if it is assigned to anything other than a node or design entity. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, Mercury^™, Stratix^™, and Stratix^™ GX devices.

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