Devices

EP1C6 Devices



The EP1C6, a member of the Cyclone device family, provides 6,523 registers; 92,160 memory bits; and 5,980 logic elements. The Cyclone device meets the low-voltage requirements of 1.8-V applications and supports multiple I/O standards including LVDS, LVTTL, LVCMOS, PCI, SSTL-3 Class I & II, and SSTL-2 Class I & II.

The EP1C6 is available in 144-pin TQFP packages with 92 I/O pins, 240-pin QFP packages with 181 I/O pins, and 256-pin FineLine BGA® packages  (See Note (12)). The device has 5,980 logic elements grouped into 598 LABs. These LABs are arranged into 20 rows and 32 columns. The embedded memory consists of one column of M4K memory blocks, containing a total of 92,160 RAM bits. Each M4K block can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers.

Each I/O element contains a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. The I/O element contains individual input, output, and output enable registers. The input register provides fast setup times, the output register provides fast clock-to-output times, and the output enable register provides fast clock-to-output enable times. The EP1C6 also contains four dedicated clock pins and eight dual-purpose clock pins for large fan-out control signals. In addition, the EP1C6 contains two phase-locked loops (PLLs), which provide general purpose clocking with clock multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support.

The EP1C6 also supports ICR and JTAG BST. The EP1C12 JTAG Instruction Register length is 10; the Boundary-Scan Register length is 194; and the JTAG ID code is 0x020820DD.

NOTE Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to the current Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP1C6 device, refer to the current Cyclone Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site.

The following table displays the pin-out information for EP1C6 devices:

 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Row I/O 0 LVDS14p/INIT_DONE 4 1 IOC_X0_Y20_N0 1 1 - DM1L
Row I/O 1 LVDS14n 4 1 IOC_X0_Y20_N1 2 2 - DQ1L0
Row I/O 2 LVDS13p/CLKUSR 4 1 IOC_X0_Y19_N0 3 3 - DQ1L1
Row I/O 3 LVDS13n 4 1 IOC_X0_Y19_N1 4 4 - -
Row I/O 4 VREF0B1 - 1 IOC_X0_Y19_N2 5 5 - -
Row I/O 5 - 4 1 IOC_X0_Y18_N0 6 6 - DQ1L2
Row I/O 6 LVDS12p 4 1 IOC_X0_Y18_N1 7 7 DQ0L0 DQ1L3
Row I/O 7 LVDS12n 4 1 IOC_X0_Y18_N2 8 - DQ0L1 -
Row I/O 8 DPCLK1 4 1 IOC_X0_Y17_N0 11 10 DQS0L -
Row I/O 9 LVDS11p 4 1 IOC_X0_Y17_N1 12 - DQ0L2 -
Row I/O 10 LVDS11n 4 1 IOC_X0_Y17_N2 13 - DQ0L3 -
Row I/O 11 LVDS10p 4 1 IOC_X0_Y16_N0 14 - - -
Row I/O 12 LVDS10n 4 1 IOC_X0_Y16_N1 15 - - -
Row I/O 13 LVDS9p 4 1 IOC_X0_Y16_N2 16 - - -
Row I/O 14 LVDS9n 4 1 IOC_X0_Y15_N0 17 - - -
Row I/O 15 LVDS8p 4 1 IOC_X0_Y15_N1 18 - - -
Row I/O 16 LVDS8n 4 1 IOC_X0_Y14_N0 19 - - -
Row I/O 17 LVDS7p 4 1 IOC_X0_Y14_N1 20 - - -
Row I/O 18 LVDS7n 4 1 IOC_X0_Y14_N2 21 - DM0L -
Row I/O 19 VREF1B1 - 1 IOC_X0_Y13_N0 23 11 - -
Row I/O 20 nCSO/nCSO 19 1 IOC_X0_Y13_N1 24 12 - -
Dedicated Programming 21 DATA0 - 1 IOC_X0_Y12_N0 25 13 - -
Dedicated Programming 22 nCONFIG - 1 IOC_X0_Y12_N1 26 14 - -
Dedicated Clock 23 CLK0/LVDSCLK1p 19 1 IOC_X0_Y12_N2 28 16 - -
Dedicated Clock 24 CLK1/LVDSCLK1n 19 1 IOC_X0_Y11_N0 29 17 - -
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Dedicated Programming 25 nCEO - 1 IOC_X0_Y11_N1 32 20 - -
Dedicated Programming 26 nCE - 1 IOC_X0_Y11_N2 33 21 - -
Dedicated Programming 27 MSEL0 - 1 IOC_X0_Y10_N0 34 22 - -
Dedicated Programming 28 MSEL1 - 1 IOC_X0_Y10_N1 35 23 - -
Dedicated Programming 29 DCLK - 1 IOC_X0_Y10_N2 36 24 - -
Row I/O 30 ASDO/ASDO 19 1 IOC_X0_Y9_N0 37 25 - -
Row I/O 31 PLL1_OUTp 19 1 IOC_X0_Y8_N0 38 26 - -
Row I/O 32 PLL1_OUTn 19 1 IOC_X0_Y8_N1 39 27 - -
Row I/O 33 - 45 1 IOC_X0_Y7_N0 41 - - -
Row I/O 34 LVDS6p 45 1 IOC_X0_Y7_N1 42 - - -
Row I/O 35 LVDS6n 45 1 IOC_X0_Y7_N2 43 - - -
Row I/O 36 LVDS5p 45 1 IOC_X0_Y6_N0 44 - - -
Row I/O 37 LVDS5n 45 1 IOC_X0_Y6_N1 45 - - -
Row I/O 38 LVDS4p 45 1 IOC_X0_Y5_N0 46 - - -
Row I/O 39 LVDS4n 45 1 IOC_X0_Y5_N1 47 - - -
Row I/O 40 LVDS3p 45 1 IOC_X0_Y4_N0 48 - DQ0L4 -
Row I/O 41 LVDS3n 45 1 IOC_X0_Y4_N1 49 - DQ0L5 -
Row I/O 42 DPCLK0 45 1 IOC_X0_Y4_N2 50 28 DQS1L DQS1L
Row I/O 43 LVDS2p 45 1 IOC_X0_Y3_N0 53 - DQ0L6 -
Row I/O 44 LVDS2n 45 1 IOC_X0_Y3_N1 54 - DQ0L7 -
Row I/O 45 VREF2B1 - 1 IOC_X0_Y3_N2 55 31 - -
Row I/O 46 - 45 1 IOC_X0_Y2_N0 56 32 - DQ1L4
Row I/O 47 LVDS1p 45 1 IOC_X0_Y2_N1 57 33 - DQ1L5
Row I/O 48 LVDS1n 45 1 IOC_X0_Y2_N2 58 34 - DQ1L6
Row I/O 49 LVDS0p 45 1 IOC_X0_Y1_N0 59 35 - DQ1L7
Row I/O 50 LVDS0n 45 1 IOC_X0_Y1_N1 60 36 - -
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Column I/O 51 LVDS71p 60 4 IOC_X2_Y0_N2 61 37 - -
Column I/O 52 LVDS71n 60 4 IOC_X2_Y0_N1 62 38 - -
Column I/O 53 LVDS70p 60 4 IOC_X2_Y0_N0 63 - - -
Column I/O 54 LVDS70n 60 4 IOC_X4_Y0_N2 64 - - -
Column I/O 55 LVDS69p 60 4 IOC_X4_Y0_N1 65 39 - DQ1B7
Column I/O 56 LVDS69n 60 4 IOC_X4_Y0_N0 66 40 - DQ1B6
Column I/O 57 LVDS68p 60 4 IOC_X6_Y0_N2 67 41 DQ1B7 DQ1B5
Column I/O 58 LVDS68n 60 4 IOC_X6_Y0_N1 68 42 DQ1B6 DQ1B4
Column I/O 59 DPCLK7 60 4 IOC_X6_Y0_N0 73 47 DQS1B DQS1B
Column I/O 60 VREF2B4 - 4 IOC_X8_Y0_N2 74 48 - -
Column I/O 61 LVDS67p 60 4 IOC_X8_Y0_N1 75 49 - -
Column I/O 62 LVDS67n 60 4 IOC_X8_Y0_N0 76 - DQ1B5 -
Column I/O 63 LVDS66p 60 4 IOC_X10_Y0_N2 77 - DQ1B4 -
Column I/O 64 LVDS66n 60 4 IOC_X10_Y0_N1 78 - - -
Column I/O 65 - 60 4 IOC_X10_Y0_N0 79 - - -
Column I/O 66 LVDS65p 60 4 IOC_X12_Y0_N2 80 - - -
Column I/O 67 LVDS65n 60 4 IOC_X12_Y0_N1 81 - - -
Column I/O 68 LVDS64p 60 4 IOC_X12_Y0_N0 82 - - -
Column I/O 69 LVDS64n 60 4 IOC_X14_Y0_N2 83 - - -
Column I/O 70 LVDS63p 60 4 IOC_X14_Y0_N1 84 50 - -
Column I/O 71 LVDS63n 60 4 IOC_X14_Y0_N0 85 51 - -
Column I/O 72 LVDS62p 75 4 IOC_X16_Y0_N2 86 52 - -
Column I/O 73 LVDS62n 75 4 IOC_X16_Y0_N1 87 53 - -
Column I/O 74 - 75 4 IOC_X16_Y0_N0 88 - - -
Column I/O 75 VREF1B4 - 4 IOC_X20_Y0_N2 93 56 - -
Column I/O 76 LVDS61p 75 4 IOC_X20_Y0_N1 94 57 DM1B DM1B
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Column I/O 77 LVDS61n 75 4 IOC_X20_Y0_N0 95 58 - -
Column I/O 78 LVDS60p 75 4 IOC_X22_Y0_N2 96 - - -
Column I/O 79 LVDS60n 75 4 IOC_X22_Y0_N1 97 - - -
Column I/O 80 LVDS59p 75 4 IOC_X22_Y0_N0 98 - - -
Column I/O 81 LVDS59n 75 4 IOC_X24_Y0_N2 99 59 - -
Column I/O 82 LVDS58p 75 4 IOC_X24_Y0_N1 100 - - -
Column I/O 83 LVDS58n 75 4 IOC_X24_Y0_N0 101 - - -
Column I/O 84 LVDS57p 89 4 IOC_X26_Y0_N2 102 - - -
Column I/O 85 LVDS57n 89 4 IOC_X26_Y0_N1 103 - - -
Column I/O 86 LVDS56p 89 4 IOC_X26_Y0_N0 104 - - -
Column I/O 87 LVDS56n 89 4 IOC_X28_Y0_N2 105 - - -
Column I/O 88 - 89 4 IOC_X28_Y0_N1 106 60 - -
Column I/O 89 VREF0B4 - 4 IOC_X28_Y0_N0 107 61 - -
Column I/O 90 DPCLK6 89 4 IOC_X30_Y0_N2 108 62 DQS0B DQS0B
Column I/O 91 LVDS55p 89 4 IOC_X30_Y0_N1 113 67 DQ1B3 DQ1B3
Column I/O 92 LVDS55n 89 4 IOC_X30_Y0_N0 114 68 DQ1B2 DQ1B2
Column I/O 93 LVDS54p 89 4 IOC_X32_Y0_N2 115 69 DQ1B1 DQ1B1
Column I/O 94 LVDS54n 89 4 IOC_X32_Y0_N1 116 70 DQ1B0 DQ1B0
Column I/O 95 LVDS53p 89 4 IOC_X32_Y0_N0 117 - - -
Column I/O 96 LVDS53n 89 4 IOC_X34_Y0_N2 118 - - -
Column I/O 97 LVDS52p 89 4 IOC_X34_Y0_N1 119 71 - -
Column I/O 98 LVDS52n 89 4 IOC_X34_Y0_N0 120 72 - -
Row I/O 99 LVDS51n 105 3 IOC_X35_Y1_N1 121 73 - -
Row I/O 100 LVDS51p 105 3 IOC_X35_Y1_N0 122 74 - -
Row I/O 101 LVDS50n 105 3 IOC_X35_Y2_N2 123 75 - -
Row I/O 102 LVDS50p 105 3 IOC_X35_Y2_N1 124 76 - -
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Row I/O 103 LVDS49n 105 3 IOC_X35_Y2_N0 125 77 DQ1R7 DQ1R7
Row I/O 104 LVDS49p 105 3 IOC_X35_Y3_N2 126 78 - -
Row I/O 105 VREF2B3 - 3 IOC_X35_Y3_N1 127 79 - -
Row I/O 106 DQ1R6 105 3 IOC_X35_Y3_N0 128 - - -
Row I/O 107 DPCLK5 105 3 IOC_X35_Y4_N2 131 82 DQS1R DQS1R
Row I/O 108 LVDS48n 105 3 IOC_X35_Y4_N1 132 83 DQ1R5 DQ1R5
Row I/O 109 LVDS48p 105 3 IOC_X35_Y4_N0 133 84 DQ1R4 DQ1R4
Row I/O 110 LVDS47n 105 3 IOC_X35_Y5_N1 134 85 - DM1R
Row I/O 111 LVDS47p 105 3 IOC_X35_Y5_N0 135 - - -
Row I/O 112 LVDS46n 105 3 IOC_X35_Y6_N1 136 - - -
Row I/O 113 LVDS46p 105 3 IOC_X35_Y6_N0 137 - - -
Row I/O 114 LVDS45n 105 3 IOC_X35_Y7_N1 138 - - -
Row I/O 115 LVDS45p 105 3 IOC_X35_Y7_N0 139 - - -
Row I/O 116 LVDS44n 105 3 IOC_X35_Y8_N1 140 - - -
Row I/O 117 LVDS44p 105 3 IOC_X35_Y8_N0 141 - - -
Row I/O 118 PLL2_OUTn 128 3 IOC_X35_Y9_N1 143 - - -
Row I/O 119 PLL2_OUTp 128 3 IOC_X35_Y9_N0 144 - - -
Dedicated Programming 120 CONF_DONE - 3 IOC_X35_Y10_N2 145 86 - -
Dedicated Programming 121 nSTATUS - 3 IOC_X35_Y10_N1 146 87 - -
JTAG 122 TCK - 3 IOC_X35_Y10_N0 147 88 - -
JTAG 123 TMS - 3 IOC_X35_Y11_N1 148 89 - -
JTAG 124 TDO - 3 IOC_X35_Y11_N0 149 90 - -
Dedicated Clock 125 CLK3/LVDSCLK2n 128 3 IOC_X35_Y12_N2 152 92 - -
Dedicated Clock 126 CLK2/LVDSCLK2p 128 3 IOC_X35_Y12_N1 153 93 - -
JTAG 127 TDI - 3 IOC_X35_Y12_N0 155 95 - -
Row I/O 128 VREF1B3 - 3 IOC_X35_Y13_N2 156 96 - -
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Row I/O 129 LVDS43n 145 3 IOC_X35_Y13_N1 158 - DM1R -
Row I/O 130 LVDS43p 145 3 IOC_X35_Y13_N0 159 - - -
Row I/O 131 LVDS42n 145 3 IOC_X35_Y14_N1 160 - - -
Row I/O 132 LVDS42p 145 3 IOC_X35_Y14_N0 161 - - -
Row I/O 133 LVDS41n 145 3 IOC_X35_Y15_N2 162 - - -
Row I/O 134 LVDS41p 145 3 IOC_X35_Y15_N1 163 - - -
Row I/O 135 LVDS40n 145 3 IOC_X35_Y15_N0 164 - - -
Row I/O 136 LVDS40p 145 3 IOC_X35_Y16_N2 165 - - -
Row I/O 137 LVDS39n 145 3 IOC_X35_Y16_N1 166 - - -
Row I/O 138 LVDS39p 145 3 IOC_X35_Y16_N0 167 97 - DQ1R3
Row I/O 139 LVDS38n 145 3 IOC_X35_Y17_N2 168 98 - DQ1R2
Row I/O 140 LVDS38p 145 3 IOC_X35_Y17_N1 169 99 DQ1R3 DQ1R1
Row I/O 141 DPCLK4 145 3 IOC_X35_Y17_N0 170 100 DQS0R DQS0R
Row I/O 142 LVDS37n 145 3 IOC_X35_Y18_N2 173 - DQ1R2 -
Row I/O 143 LVDS37p 145 3 IOC_X35_Y18_N1 174 - DQ1R1 -
Row I/O 144 - 145 3 IOC_X35_Y18_N0 175 103 DQ1R0 DQ1R0
Row I/O 145 VREF0B3 - 3 IOC_X35_Y19_N2 176 104 - -
Row I/O 146 LVDS36n 145 3 IOC_X35_Y19_N1 177 105 - -
Row I/O 147 LVDS36p 145 3 IOC_X35_Y19_N0 178 106 - -
Row I/O 148 LVDS35n 145 3 IOC_X35_Y20_N1 179 107 - -
Row I/O 149 LVDS35p 145 3 IOC_X35_Y20_N0 180 108 - -
Column I/O 150 LVDS34n 159 2 IOC_X34_Y21_N0 181 109 - -
Column I/O 151 LVDS34p 159 2 IOC_X34_Y21_N1 182 110 - -
Column I/O 152 LVDS33n 159 2 IOC_X34_Y21_N2 183 - - -
Column I/O 153 LVDS33p 159 2 IOC_X32_Y21_N0 184 - - -
Column I/O 154 LVDS32n 159 2 IOC_X32_Y21_N1 185 111 DQ0T0 DQ0T0
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Column I/O 155 LVDS32p 159 2 IOC_X32_Y21_N2 186 112 DQ0T1 DQ0T1
Column I/O 156 LVDS31n 159 2 IOC_X30_Y21_N0 187 113 DQ0T2 DQ0T2
Column I/O 157 LVDS31p 159 2 IOC_X30_Y21_N1 188 114 DQ0T3 DQ0T3
Column I/O 158 DPCLK3 159 2 IOC_X30_Y21_N2 193 119 DQS0T DQS0T
Column I/O 159 VREF0B2 - 2 IOC_X28_Y21_N0 194 120 - -
Column I/O 160 - 159 2 IOC_X28_Y21_N1 195 121 - -
Column I/O 161 LVDS30n 159 2 IOC_X28_Y21_N2 196 - - -
Column I/O 162 LVDS30p 159 2 IOC_X26_Y21_N0 197 - - -
Column I/O 163 LVDS29n 159 2 IOC_X26_Y21_N1 198 - - -
Column I/O 164 LVDS29p 159 2 IOC_X26_Y21_N2 199 - - -
Column I/O 165 LVDS28n 173 2 IOC_X24_Y21_N0 200 - - -
Column I/O 166 LVDS28p 173 2 IOC_X24_Y21_N1 201 - - -
Column I/O 167 LVDS27n 173 2 IOC_X24_Y21_N2 202 122 - -
Column I/O 168 LVDS27p 173 2 IOC_X22_Y21_N0 203 - - -
Column I/O 169 LVDS26n 173 2 IOC_X22_Y21_N1 204 - - -
Column I/O 170 LVDS26p 173 2 IOC_X22_Y21_N2 205 - - -
Column I/O 171 LVDS25n 173 2 IOC_X20_Y21_N0 206 123 DM0T DM0T
Column I/O 172 LVDS25p 173 2 IOC_X20_Y21_N1 207 124 - -
Column I/O 173 VREF1B2 - 2 IOC_X20_Y21_N2 208 125 - -
Column I/O 174 - 173 2 IOC_X16_Y21_N0 213 - - -
Column I/O 175 LVDS24n 173 2 IOC_X16_Y21_N1 214 128 - -
Column I/O 176 LVDS24p 173 2 IOC_X16_Y21_N2 215 129 - -
Column I/O 177 LVDS23n 188 2 IOC_X14_Y21_N0 216 130 - -
Column I/O 178 LVDS23p 188 2 IOC_X14_Y21_N1 217 131 - -
Column I/O 179 LVDS22n 188 2 IOC_X14_Y21_N2 218 - - -
Column I/O 180 LVDS22p 188 2 IOC_X12_Y21_N0 219 - - -
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
240-Pin
PQFP
144-Pin
TQFP
240-pin
DQ/DQS
144-pin
DQ/DQS
    Note (10)              

 
Column I/O 181 LVDS21n 188 2 IOC_X12_Y21_N1 220 - - -
Column I/O 182 LVDS21p 188 2 IOC_X12_Y21_N2 221 - - -
Column I/O 183 - 188 2 IOC_X10_Y21_N0 222 - - -
Column I/O 184 LVDS20n 188 2 IOC_X10_Y21_N1 223 - - -
Column I/O 185 LVDS20p 188 2 IOC_X10_Y21_N2 224 - - -
Column I/O 186 LVDS19n 188 2 IOC_X8_Y21_N0 225 - - -
Column I/O 187 LVDS19p 188 2 IOC_X8_Y21_N1 226 132 - -
Column I/O 188 VREF2B2 - 2 IOC_X8_Y21_N2 227 133 - -
Column I/O 189 DPCLK2 188 2 IOC_X6_Y21_N0 228 134 DQS1T DQS1T
Column I/O 190 LVDS18n 188 2 IOC_X6_Y21_N1 233 139 DQ0T4 DQ0T4
Column I/O 191 LVDS18p 188 2 IOC_X6_Y21_N2 234 140 DQ0T5 DQ0T5
Column I/O 192 LVDS17n 188 2 IOC_X4_Y21_N0 235 141 DQ0T6 DQ0T6
Column I/O 193 LVDS17p 188 2 IOC_X4_Y21_N1 236 142 DQ0T7 DQ0T7
Column I/O 194 LVDS16n 188 2 IOC_X4_Y21_N2 237 - - -
Column I/O 195 LVDS16p 188 2 IOC_X2_Y21_N0 238 - - -
Column I/O 196 LVDS15n/DEV_OE 188 2 IOC_X2_Y21_N1 239 143 - -
Column I/O 197 LVDS15p/DEV_CLRn 188 2 IOC_X2_Y21_N2 240 144 - -


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