Devices

EP1C20 Devices



The EP1C20, a member of the Cyclone device family, provides 20,912 registers; 294,912 memory bits; and 20,060 logic elements. The Cyclone device meets the low-voltage requirements of 1.8-V applications and supports multiple I/O standards including LVDS, LVTTL, LVCMOS, PCI, SSTL-3 Class I & II, and SSTL-2 Class I & II.

The EP1C20 is available in 324-pin FineLine BGA® packages with 229 I/O pins and 400-pin FineLine BGA packages with 297 I/O pins. The device has 20,060 logic elements grouped into 2,006 LABs. These LABs are arranged into 32 rows and 64 columns. The embedded memory consists of two columns of M4K memory blocks, containing a total of 294,912 RAM bits. Each M4K block can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers.

Each I/O element contains a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. The I/O element contains individual input, output, and output enable registers. The input register provides fast setup times, the output register provides fast clock-to-output times, and the output enable register provides fast clock-to-output enable times. The EP1C20 also contains four dedicated clock pins and eight dual-purpose clock pins for large fan-out control signals. In addition, the EP1C20 contains two phase-locked loops (PLLs), which provide general purpose clocking with clock multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support.

The EP1C20 also supports ICR and JTAG BST. The EP1C20 JTAG Instruction Register length is 10; the Boundary-Scan Register length is 310; and the JTAG ID code is 0x020840DD.

NOTE Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to the current Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP1C20 device, refer to the current Cyclone Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site.

The following table displays the pin-out information for EP1C20 devices:

 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 0 LVDS31p/INIT_DONE 4 1 IOC_X0_Y32_N0 C3 C3
Row I/O 1 LVDS31n 4 1 IOC_X0_Y32_N1 C2 C2
Row I/O 2 LVDS30p/CLKUSR 4 1 IOC_X0_Y31_N0 D3 D3
Row I/O 3 LVDS30n 4 1 IOC_X0_Y31_N1 D2 D2
Row I/O 4 VREF0B1 - 1 IOC_X0_Y31_N2 D4 D4
Row I/O 5 - 4 1 IOC_X0_Y30_N0 D1 D1
Row I/O 6 LVDS29p/DQ0L0 4 1 IOC_X0_Y30_N1 E3 E4
Row I/O 7 LVDS29n/DQ0L1 4 1 IOC_X0_Y30_N2 E2 E5
Row I/O 8 DPCLK1/DQS0L 4 1 IOC_X0_Y29_N0 F1 F3
Row I/O 9 LVDS28p/DQ0L2 4 1 IOC_X0_Y29_N1 E4 E3
Row I/O 10 LVDS28n/DQ0L3 4 1 IOC_X0_Y29_N2 E5 E2
Row I/O 11 LVDS27p 4 1 IOC_X0_Y28_N0 F2 F4
Row I/O 12 LVDS27n 4 1 IOC_X0_Y28_N1 F3 F5
Row I/O 13 LVDS26p 4 1 IOC_X0_Y28_N2 F4 F2
Row I/O 14 LVDS26n 4 1 IOC_X0_Y27_N0 F5 F1
Row I/O 15 LVDS25p 4 1 IOC_X0_Y27_N1 G1 F6
Row I/O 16 LVDS25n 4 1 IOC_X0_Y27_N2 G2 G5
Row I/O 17 LVDS24p 4 1 IOC_X0_Y26_N0 F6 G1
Row I/O 18 LVDS24n 4 1 IOC_X0_Y26_N1 F7 G2
Row I/O 19 LVDS23p 4 1 IOC_X0_Y26_N2 G3 G6
Row I/O 20 LVDS23n/DQ0L4 4 1 IOC_X0_Y25_N0 G4 G7
Row I/O 21 LVDS22p/DQ0L5 4 1 IOC_X0_Y25_N1 G5 G3
Row I/O 22 LVDS22n/DQ0L6 4 1 IOC_X0_Y25_N2 G6 G4
Row I/O 23 DQ0L7 4 1 IOC_X0_Y24_N0 H1 H7
Row I/O 24 LVDS21p 37 1 IOC_X0_Y24_N1 H2 H1
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 25 LVDS21n 37 1 IOC_X0_Y24_N2 H3 H2
Row I/O 26 LVDS20p 37 1 IOC_X0_Y23_N0 H4 H3
Row I/O 27 LVDS20n/DM0L 37 1 IOC_X0_Y23_N1 H5 H4
Row I/O 28 LVDS19p 37 1 IOC_X0_Y22_N0 - J1
Row I/O 29 LVDS19n 37 1 IOC_X0_Y22_N1 - J2
Row I/O 30 LVDS18p 37 1 IOC_X0_Y22_N2 - H5
Row I/O 31 LVDS18n 37 1 IOC_X0_Y21_N0 - H6
Row I/O 32 LVDS17p 37 1 IOC_X0_Y21_N1 - J3
Row I/O 33 LVDS17n 37 1 IOC_X0_Y21_N2 - J4
Row I/O 34 LVDS16p 37 1 IOC_X0_Y20_N0 - J5
Row I/O 35 LVDS16n 37 1 IOC_X0_Y20_N1 - J6
Row I/O 36 - 37 1 IOC_X0_Y20_N2 - J7
Row I/O 37 VREF1B1 - 1 IOC_X0_Y19_N0 H6 J8
Row I/O 38 nCSO/nCSO 37 1 IOC_X0_Y19_N1 J1 K2
Dedicated Programming 39 DATA0 - 1 IOC_X0_Y18_N0 H7 K3
Dedicated Programming 40 nCONFIG - 1 IOC_X0_Y18_N1 J2 K1
Dedicated Clock 41 CLK0/LVDSCLK1p 37 1 IOC_X0_Y18_N2 J3 K5
Dedicated Clock 42 CLK1/LVDSCLK1n 37 1 IOC_X0_Y17_N0 J4 K6
Dedicated Programming 43 nCEO - 1 IOC_X0_Y17_N1 K2 L2
Dedicated Programming 44 nCE - 1 IOC_X0_Y17_N2 J7 L5
Dedicated Programming 45 MSEL0 - 1 IOC_X0_Y16_N0 K3 L1
Dedicated Programming 46 MSEL1 - 1 IOC_X0_Y16_N1 K7 L6
Dedicated Programming 47 DCLK - 1 IOC_X0_Y16_N2 L1 L3
Row I/O 48 ASDO/ASDO 37 1 IOC_X0_Y15_N0 K6 L4
Row I/O 49 PLL1_OUTp 37 1 IOC_X0_Y14_N0 K4 L8
Row I/O 50 PLL1_OUTn 37 1 IOC_X0_Y14_N1 K5 M8
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 51 LVDS15p 37 1 IOC_X0_Y13_N0 - M2
Row I/O 52 LVDS15n 37 1 IOC_X0_Y13_N1 - M1
Row I/O 53 LVDS14p 37 1 IOC_X0_Y13_N2 - M5
Row I/O 54 LVDS14n 37 1 IOC_X0_Y12_N0 - M6
Row I/O 55 LVDS13p 37 1 IOC_X0_Y12_N1 - M4
Row I/O 56 LVDS13n 37 1 IOC_X0_Y12_N2 - M3
Row I/O 57 LVDS12p/DM1L 37 1 IOC_X0_Y11_N0 L7 M7
Row I/O 58 LVDS12n 37 1 IOC_X0_Y11_N1 L6 N6
Row I/O 59 LVDS11p 37 1 IOC_X0_Y11_N2 L2 N1
Row I/O 60 LVDS11n 37 1 IOC_X0_Y10_N0 L3 N2
Row I/O 61 LVDS10p 37 1 IOC_X0_Y10_N1 L5 N4
Row I/O 62 LVDS10n 37 1 IOC_X0_Y10_N2 L4 N3
Row I/O 63 DQ1L0 81 1 IOC_X0_Y9_N0 M1 N5
Row I/O 64 LVDS9p 81 1 IOC_X0_Y9_N1 - N7
Row I/O 65 LVDS9n 81 1 IOC_X0_Y9_N2 - P7
Row I/O 66 LVDS8p/DQ1L1 81 1 IOC_X0_Y8_N0 M3 P2
Row I/O 67 LVDS8n/DQ1L2 81 1 IOC_X0_Y8_N1 M2 P1
Row I/O 68 LVDS7p/DQ1L3 81 1 IOC_X0_Y7_N0 M5 P6
Row I/O 69 LVDS7n 81 1 IOC_X0_Y7_N1 M4 P5
Row I/O 70 LVDS6p 81 1 IOC_X0_Y6_N0 N1 P3
Row I/O 71 LVDS6n 81 1 IOC_X0_Y6_N1 N2 P4
Row I/O 72 LVDS5p 81 1 IOC_X0_Y6_N2 M6 R1
Row I/O 73 LVDS5n 81 1 IOC_X0_Y5_N0 N7 R2
Row I/O 74 LVDS4p 81 1 IOC_X0_Y5_N1 N5 R6
Row I/O 75 LVDS4n 81 1 IOC_X0_Y5_N2 N6 R5
Row I/O 76 LVDS3p/DQ1L4 81 1 IOC_X0_Y4_N0 N3 R3
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 77 LVDS3n/DQ1L5 81 1 IOC_X0_Y4_N1 N4 R4
Row I/O 78 DPCLK0/DQS1L 81 1 IOC_X0_Y4_N2 P5 T4
Row I/O 79 LVDS2p/DQ1L6 81 1 IOC_X0_Y3_N0 P2 T2
Row I/O 80 LVDS2n/DQ1L7 81 1 IOC_X0_Y3_N1 P3 T3
Row I/O 81 VREF2B1 - 1 IOC_X0_Y3_N2 R1 U1
Row I/O 82 - 81 1 IOC_X0_Y2_N0 P4 U4
Row I/O 83 LVDS1p 81 1 IOC_X0_Y2_N1 R2 U2
Row I/O 84 LVDS1n 81 1 IOC_X0_Y2_N2 R3 U3
Row I/O 85 LVDS0p 81 1 IOC_X0_Y1_N0 T2 V2
Row I/O 86 LVDS0n 81 1 IOC_X0_Y1_N1 T3 V3
Column I/O 87 LVDS128p 96 4 IOC_X2_Y0_N1 U3 W3
Column I/O 88 LVDS128n 96 4 IOC_X2_Y0_N0 V4 Y4
Column I/O 89 LVDS127p 96 4 IOC_X4_Y0_N1 T4 V4
Column I/O 90 LVDS127n 96 4 IOC_X4_Y0_N0 U4 W4
Column I/O 91 LVDS126p/DQ1B7 96 4 IOC_X6_Y0_N1 T5 T5
Column I/O 92 LVDS126n/DQ1B6 96 4 IOC_X6_Y0_N0 U5 U5
Column I/O 93 LVDS125p 96 4 IOC_X8_Y0_N1 - V5
Column I/O 94 LVDS125n 96 4 IOC_X8_Y0_N0 - W5
Column I/O 95 DPCLK7/DQS1B 96 4 IOC_X10_Y0_N2 R4 T6
Column I/O 96 VREF2B4 - 4 IOC_X10_Y0_N1 R5 T7
Column I/O 97 LVDS124p 96 4 IOC_X10_Y0_N0 V6 W6
Column I/O 98 LVDS124n/DQ1B5 96 4 IOC_X12_Y0_N1 U6 Y6
Column I/O 99 LVDS123p/DQ1B4 96 4 IOC_X12_Y0_N0 P6 U6
Column I/O 100 LVDS123n 96 4 IOC_X14_Y0_N2 P7 V6
Column I/O 101 LVDS122p 96 4 IOC_X14_Y0_N1 T6 W7
Column I/O 102 LVDS122n 96 4 IOC_X14_Y0_N0 R6 Y7
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 103 LVDS121p/DQ1B3 96 4 IOC_X16_Y0_N1 U7 R7
Column I/O 104 LVDS121n/DQ1B2 96 4 IOC_X16_Y0_N0 V7 T8
Column I/O 105 LVDS120p/DQ1B1 96 4 IOC_X18_Y0_N1 T7 V7
Column I/O 106 LVDS120n/DQ1B0 96 4 IOC_X18_Y0_N0 R7 U7
Column I/O 107 LVDS119p 119 4 IOC_X22_Y0_N1 U8 V8
Column I/O 108 LVDS119n 119 4 IOC_X22_Y0_N0 V8 U8
Column I/O 109 LVDS118p 119 4 IOC_X24_Y0_N1 T8 W8
Column I/O 110 LVDS118n 119 4 IOC_X24_Y0_N0 R8 Y8
Column I/O 111 LVDS117p 119 4 IOC_X26_Y0_N1 U9 U9
Column I/O 112 LVDS117n 119 4 IOC_X26_Y0_N0 V9 V9
Column I/O 113 LVDS116p/DM1B 119 4 IOC_X28_Y0_N1 R9 T9
Column I/O 114 LVDS116n 119 4 IOC_X28_Y0_N0 T9 R9
Column I/O 115 LVDS115p 119 4 IOC_X30_Y0_N1 - Y9
Column I/O 116 LVDS115n 119 4 IOC_X30_Y0_N0 - W9
Column I/O 117 LVDS114p 119 4 IOC_X32_Y0_N2 - T10
Column I/O 118 LVDS114n 119 4 IOC_X32_Y0_N1 - U10
Column I/O 119 VREF1B4 - 4 IOC_X32_Y0_N0 P9 V10
Column I/O 120 LVDS113p 119 4 IOC_X34_Y0_N2 - W10
Column I/O 121 LVDS113n 119 4 IOC_X34_Y0_N1 - Y10
Column I/O 122 LVDS112p 119 4 IOC_X34_Y0_N0 U10 V11
Column I/O 123 LVDS112n 119 4 IOC_X36_Y0_N2 V10 U11
Column I/O 124 LVDS111p 119 4 IOC_X36_Y0_N1 T10 W11
Column I/O 125 LVDS111n 119 4 IOC_X36_Y0_N0 R10 Y11
Column I/O 126 - 119 4 IOC_X38_Y0_N2 - R11
Column I/O 127 LVDS110p 119 4 IOC_X38_Y0_N1 - Y12
Column I/O 128 LVDS110n 119 4 IOC_X38_Y0_N0 P10 W12
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 129 LVDS109p 119 4 IOC_X40_Y0_N1 R11 T11
Column I/O 130 LVDS109n 119 4 IOC_X40_Y0_N0 T11 T12
Column I/O 131 LVDS108p/DM0B 119 4 IOC_X42_Y0_N1 U11 U12
Column I/O 132 LVDS108n 119 4 IOC_X42_Y0_N0 V11 V12
Column I/O 133 LVDS107p 119 4 IOC_X44_Y0_N1 V12 T13
Column I/O 134 LVDS107n 119 4 IOC_X44_Y0_N0 U12 R13
Column I/O 135 LVDS106p/DQ0B7 147 4 IOC_X46_Y0_N1 T12 Y13
Column I/O 136 LVDS106n/DQ0B6 147 4 IOC_X46_Y0_N0 R12 W13
Column I/O 137 LVDS105p/DQ0B5 147 4 IOC_X48_Y0_N1 V13 U13
Column I/O 138 LVDS105n/DQ0B4 147 4 IOC_X48_Y0_N0 U13 V13
Column I/O 139 LVDS104p 147 4 IOC_X52_Y0_N1 T13 R14
Column I/O 140 LVDS104n 147 4 IOC_X52_Y0_N0 R13 T14
Column I/O 141 LVDS103p 147 4 IOC_X54_Y0_N1 - W14
Column I/O 142 LVDS103n 147 4 IOC_X54_Y0_N0 - Y14
Column I/O 143 LVDS102p 147 4 IOC_X56_Y0_N1 - U14
Column I/O 144 LVDS102n 147 4 IOC_X56_Y0_N0 - V14
Column I/O 145 LVDS101p 147 4 IOC_X58_Y0_N1 - V15
Column I/O 146 LVDS101n 147 4 IOC_X58_Y0_N0 P12 U15
Column I/O 147 VREF0B4 - 4 IOC_X60_Y0_N1 P13 Y15
Column I/O 148 DPCLK6/DQS0B 147 4 IOC_X60_Y0_N0 U14 W15
Column I/O 149 LVDS100p 147 4 IOC_X62_Y0_N1 - T15
Column I/O 150 LVDS100n 147 4 IOC_X62_Y0_N0 - T16
Column I/O 151 LVDS99p/DQ0B3 147 4 IOC_X64_Y0_N1 T14 W16
Column I/O 152 LVDS99n/DQ0B2 147 4 IOC_X64_Y0_N0 R14 V16
Column I/O 153 LVDS98p/DQ0B1 147 4 IOC_X66_Y0_N1 V15 V17
Column I/O 154 LVDS98n/DQ0B0 147 4 IOC_X66_Y0_N0 U15 U16
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 155 LVDS97p 147 4 IOC_X68_Y0_N1 U16 Y17
Column I/O 156 LVDS97n 147 4 IOC_X68_Y0_N0 T15 W17
Row I/O 157 LVDS96n 163 3 IOC_X69_Y1_N1 T16 W18
Row I/O 158 LVDS96p 163 3 IOC_X69_Y1_N0 T17 V18
Row I/O 159 LVDS95n 163 3 IOC_X69_Y2_N2 R17 V19
Row I/O 160 LVDS95p 163 3 IOC_X69_Y2_N1 R18 U20
Row I/O 161 LVDS94n/DQ1R7 163 3 IOC_X69_Y2_N0 R15 U18
Row I/O 162 LVDS94p 163 3 IOC_X69_Y3_N2 R16 U19
Row I/O 163 VREF2B3 - 3 IOC_X69_Y3_N1 P16 U17
Row I/O 164 DQ1R6 163 3 IOC_X69_Y3_N0 P17 T18
Row I/O 165 DPCLK5/DQS1R 163 3 IOC_X69_Y4_N2 P15 T19
Row I/O 166 LVDS93n/DQ1R5 163 3 IOC_X69_Y4_N1 P14 T17
Row I/O 167 LVDS93p/DQ1R4 163 3 IOC_X69_Y4_N0 N14 R16
Row I/O 168 LVDS92n 163 3 IOC_X69_Y5_N2 N18 R19
Row I/O 169 LVDS92p 163 3 IOC_X69_Y5_N1 N17 R20
Row I/O 170 LVDS91n 163 3 IOC_X69_Y5_N0 N13 R17
Row I/O 171 LVDS91p 163 3 IOC_X69_Y6_N2 N12 R18
Row I/O 172 LVDS90n 163 3 IOC_X69_Y6_N1 N16 R15
Row I/O 173 LVDS90p 163 3 IOC_X69_Y6_N0 N15 P14
Row I/O 174 LVDS89n 163 3 IOC_X69_Y7_N1 M18 P18
Row I/O 175 LVDS89p/DQ1R3 163 3 IOC_X69_Y7_N0 M17 P17
Row I/O 176 LVDS88n/DQ1R2 163 3 IOC_X69_Y8_N1 M14 P16
Row I/O 177 LVDS88p/DQ1R1 163 3 IOC_X69_Y8_N0 M15 P15
Row I/O 178 LVDS87n 163 3 IOC_X69_Y9_N2 - P19
Row I/O 179 LVDS87p 163 3 IOC_X69_Y9_N1 - P20
Row I/O 180 DQ1R0 163 3 IOC_X69_Y9_N0 M16 N14
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 181 LVDS86n 204 3 IOC_X69_Y10_N2 L18 N18
Row I/O 182 LVDS86p 204 3 IOC_X69_Y10_N1 L17 N17
Row I/O 183 LVDS85n 204 3 IOC_X69_Y10_N0 M13 N19
Row I/O 184 LVDS85p 204 3 IOC_X69_Y11_N2 L13 N20
Row I/O 185 LVDS84n/DM1R 204 3 IOC_X69_Y11_N1 L16 N16
Row I/O 186 LVDS84p 204 3 IOC_X69_Y11_N0 L15 N15
Row I/O 187 LVDS83n 204 3 IOC_X69_Y12_N2 - M18
Row I/O 188 LVDS83p 204 3 IOC_X69_Y12_N1 - M17
Row I/O 189 LVDS82n 204 3 IOC_X69_Y12_N0 - M15
Row I/O 190 LVDS82p 204 3 IOC_X69_Y13_N1 - M16
Row I/O 191 LVDS81n 204 3 IOC_X69_Y13_N0 - M20
Row I/O 192 LVDS81p 204 3 IOC_X69_Y14_N1 - M19
Row I/O 193 - 204 3 IOC_X69_Y14_N0 L14 M14
Row I/O 194 PLL2_OUTn 204 3 IOC_X69_Y15_N1 K16 M13
Row I/O 195 PLL2_OUTp 204 3 IOC_X69_Y15_N0 K15 L13
Dedicated Programming 196 CONF_DONE - 3 IOC_X69_Y16_N2 K17 L18
Dedicated Programming 197 nSTATUS - 3 IOC_X69_Y16_N1 L12 L17
JTAG 198 TCK - 3 IOC_X69_Y16_N0 K18 L19
JTAG 199 TMS - 3 IOC_X69_Y17_N1 K14 L16
JTAG 200 TDO - 3 IOC_X69_Y17_N0 K13 L20
Dedicated Clock 201 CLK3/LVDSCLK2n 204 3 IOC_X69_Y18_N2 J16 K14
Dedicated Clock 202 CLK2/LVDSCLK2p 204 3 IOC_X69_Y18_N1 J15 L14
JTAG 203 TDI - 3 IOC_X69_Y18_N0 J17 K18
Row I/O 204 VREF1B3 - 3 IOC_X69_Y19_N2 J14 K19
Row I/O 205 - 204 3 IOC_X69_Y19_N1 - J13
Row I/O 206 LVDS80n 204 3 IOC_X69_Y19_N0 - K16
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 207 LVDS80p 204 3 IOC_X69_Y20_N2 - K15
Row I/O 208 LVDS79n 204 3 IOC_X69_Y20_N1 - J18
Row I/O 209 LVDS79p 204 3 IOC_X69_Y20_N0 - J17
Row I/O 210 LVDS78n 204 3 IOC_X69_Y21_N2 - J14
Row I/O 211 LVDS78p 204 3 IOC_X69_Y21_N1 - H14
Row I/O 212 LVDS77n 204 3 IOC_X69_Y21_N0 - J20
Row I/O 213 LVDS77p 204 3 IOC_X69_Y22_N2 - J19
Row I/O 214 LVDS76n 204 3 IOC_X69_Y22_N1 J13 J15
Row I/O 215 LVDS76p/DM0R 204 3 IOC_X69_Y22_N0 H13 J16
Row I/O 216 LVDS75n 204 3 IOC_X69_Y23_N1 H14 H20
Row I/O 217 LVDS75p 204 3 IOC_X69_Y23_N0 H15 H19
Row I/O 218 LVDS74n 204 3 IOC_X69_Y24_N2 H16 H17
Row I/O 219 LVDS74p 204 3 IOC_X69_Y24_N1 H17 H18
Row I/O 220 DQ0R7 239 3 IOC_X69_Y24_N0 H18 H16
Row I/O 221 LVDS73n/DQ0R6 239 3 IOC_X69_Y25_N2 G18 G17
Row I/O 222 LVDS73p/DQ0R5 239 3 IOC_X69_Y25_N1 G17 G18
Row I/O 223 LVDS72n/DQ0R4 239 3 IOC_X69_Y25_N0 G13 H15
Row I/O 224 LVDS72p 239 3 IOC_X69_Y26_N2 G14 G14
Row I/O 225 LVDS71n 239 3 IOC_X69_Y26_N1 G15 G19
Row I/O 226 LVDS71p 239 3 IOC_X69_Y26_N0 G16 G20
Row I/O 227 LVDS70n 239 3 IOC_X69_Y27_N2 G12 G15
Row I/O 228 LVDS70p 239 3 IOC_X69_Y27_N1 F12 G16
Row I/O 229 LVDS69n 239 3 IOC_X69_Y27_N0 F18 F20
Row I/O 230 LVDS69p 239 3 IOC_X69_Y28_N2 F17 F19
Row I/O 231 LVDS68n 239 3 IOC_X69_Y28_N1 F13 F15
Row I/O 232 LVDS68p 239 3 IOC_X69_Y28_N0 F14 F16
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Row I/O 233 LVDS67n 239 3 IOC_X69_Y29_N2 F16 E19
Row I/O 234 LVDS67p/DQ0R3 239 3 IOC_X69_Y29_N1 F15 E18
Row I/O 235 DPCLK4/DQS0R 239 3 IOC_X69_Y29_N0 E17 F18
Row I/O 236 LVDS66n/DQ0R2 239 3 IOC_X69_Y30_N2 E16 F17
Row I/O 237 LVDS66p/DQ0R1 239 3 IOC_X69_Y30_N1 E15 E17
Row I/O 238 DQ0R0 239 3 IOC_X69_Y30_N0 D18 D20
Row I/O 239 VREF0B3 - 3 IOC_X69_Y31_N2 E14 D17
Row I/O 240 LVDS65n 239 3 IOC_X69_Y31_N1 D16 D19
Row I/O 241 LVDS65p 239 3 IOC_X69_Y31_N0 D15 D18
Row I/O 242 LVDS64n 239 3 IOC_X69_Y32_N1 C17 C19
Row I/O 243 LVDS64p 239 3 IOC_X69_Y32_N0 D17 C18
Column I/O 244 LVDS63n 253 2 IOC_X68_Y33_N0 C16 C17
Column I/O 245 LVDS63p 253 2 IOC_X68_Y33_N1 B16 B18
Column I/O 246 LVDS62n/DQ0T0 253 2 IOC_X66_Y33_N0 B15 B17
Column I/O 247 LVDS62p/DQ0T1 253 2 IOC_X66_Y33_N1 A15 A17
Column I/O 248 LVDS61n/DQ0T2 253 2 IOC_X64_Y33_N0 C15 C16
Column I/O 249 LVDS61p/DQ0T3 253 2 IOC_X64_Y33_N1 D14 B16
Column I/O 250 LVDS60n 253 2 IOC_X62_Y33_N0 - D16
Column I/O 251 LVDS60p 253 2 IOC_X62_Y33_N1 - E16
Column I/O 252 DPCLK3/DQS0T 253 2 IOC_X60_Y33_N0 B14 C15
Column I/O 253 VREF0B2 - 2 IOC_X60_Y33_N1 C14 D15
Column I/O 254 LVDS59n 253 2 IOC_X58_Y33_N0 E13 B15
Column I/O 255 LVDS59p 253 2 IOC_X58_Y33_N1 - A15
Column I/O 256 LVDS58n 253 2 IOC_X56_Y33_N0 - E15
Column I/O 257 LVDS58p 253 2 IOC_X56_Y33_N1 - F14
Column I/O 258 LVDS57n 253 2 IOC_X54_Y33_N0 - A14
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 259 LVDS57p 253 2 IOC_X54_Y33_N1 - B14
Column I/O 260 LVDS56n 253 2 IOC_X52_Y33_N0 B13 E14
Column I/O 261 LVDS56p 253 2 IOC_X52_Y33_N1 A13 E13
Column I/O 262 LVDS55n/DQ0T4 253 2 IOC_X48_Y33_N0 D13 C14
Column I/O 263 LVDS55p/DQ0T5 253 2 IOC_X48_Y33_N1 C13 D14
Column I/O 264 LVDS54n/DQ0T6 253 2 IOC_X46_Y33_N0 D12 A13
Column I/O 265 LVDS54p/DQ0T7 253 2 IOC_X46_Y33_N1 C12 B13
Column I/O 266 LVDS53n 281 2 IOC_X44_Y33_N0 B12 C13
Column I/O 267 LVDS53p 281 2 IOC_X44_Y33_N1 A12 D13
Column I/O 268 LVDS52n 281 2 IOC_X42_Y33_N0 C11 E12
Column I/O 269 LVDS52p 281 2 IOC_X42_Y33_N1 D11 F12
Column I/O 270 LVDS51n 281 2 IOC_X40_Y33_N0 B11 A12
Column I/O 271 LVDS51p/DM0T 281 2 IOC_X40_Y33_N1 A11 B12
Column I/O 272 LVDS50n 281 2 IOC_X38_Y33_N0 E11 D12
Column I/O 273 LVDS50p 281 2 IOC_X38_Y33_N1 - C12
Column I/O 274 - 281 2 IOC_X38_Y33_N2 - E11
Column I/O 275 LVDS49n 281 2 IOC_X36_Y33_N0 C10 A11
Column I/O 276 LVDS49p 281 2 IOC_X36_Y33_N1 D10 B11
Column I/O 277 LVDS48n 281 2 IOC_X36_Y33_N2 B10 D11
Column I/O 278 LVDS48p 281 2 IOC_X34_Y33_N0 A10 C11
Column I/O 279 LVDS47n 281 2 IOC_X34_Y33_N1 - D10
Column I/O 280 LVDS47p 281 2 IOC_X34_Y33_N2 - C10
Column I/O 281 VREF1B2 - 2 IOC_X32_Y33_N0 E10 F10
Column I/O 282 LVDS46n 281 2 IOC_X32_Y33_N1 - A10
Column I/O 283 LVDS46p 281 2 IOC_X32_Y33_N2 - B10
Column I/O 284 LVDS45n 281 2 IOC_X30_Y33_N0 - E10
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 285 LVDS45p 281 2 IOC_X30_Y33_N1 - E9
Column I/O 286 LVDS44n/DM1T 281 2 IOC_X28_Y33_N0 D9 C9
Column I/O 287 LVDS44p 281 2 IOC_X28_Y33_N1 C9 D9
Column I/O 288 LVDS43n 281 2 IOC_X26_Y33_N0 A9 A9
Column I/O 289 LVDS43p 281 2 IOC_X26_Y33_N1 B9 B9
Column I/O 290 LVDS42n 281 2 IOC_X24_Y33_N0 D8 C8
Column I/O 291 LVDS42p 281 2 IOC_X24_Y33_N1 C8 D8
Column I/O 292 LVDS41n 281 2 IOC_X22_Y33_N0 A8 A8
Column I/O 293 LVDS41p 281 2 IOC_X22_Y33_N1 B8 B8
Column I/O 294 LVDS40n/DQ1T0 304 2 IOC_X18_Y33_N0 E8 E8
Column I/O 295 LVDS40p/DQ1T1 304 2 IOC_X18_Y33_N1 E7 F8
Column I/O 296 LVDS39n/DQ1T2 304 2 IOC_X16_Y33_N0 A7 C7
Column I/O 297 LVDS39p/DQ1T3 304 2 IOC_X16_Y33_N1 B7 D7
Column I/O 298 LVDS38n 304 2 IOC_X14_Y33_N0 D7 A7
Column I/O 299 LVDS38p 304 2 IOC_X14_Y33_N1 C7 B7
Column I/O 300 LVDS37n 304 2 IOC_X14_Y33_N2 E6 E7
Column I/O 301 LVDS37p 304 2 IOC_X12_Y33_N0 D6 F7
Column I/O 302 LVDS36n 304 2 IOC_X12_Y33_N1 B6 A6
Column I/O 303 LVDS36p 304 2 IOC_X10_Y33_N0 C6 B6
Column I/O 304 VREF2B2 - 2 IOC_X10_Y33_N1 A6 E6
Column I/O 305 DPCLK2/DQS1T 304 2 IOC_X10_Y33_N2 B5 C6
Column I/O 306 LVDS35n 304 2 IOC_X8_Y33_N0 - B5
Column I/O 307 LVDS35p 304 2 IOC_X8_Y33_N1 - C5
Column I/O 308 LVDS34n/DQ1T4 304 2 IOC_X6_Y33_N0 C5 D6
Column I/O 309 LVDS34p/DQ1T5 304 2 IOC_X6_Y33_N1 D5 D5
Column I/O 310 LVDS33n/DQ1T6 304 2 IOC_X4_Y33_N0 A4 A4
 
Function Pad
No.
Secondary
Function
VRef
Pad
I/O
Bank
Pad
Location
324-Pin
FineLine
400-Pin
FineLine
    Note (10)          

 
Column I/O 311 LVDS33p/DQ1T7 304 2 IOC_X4_Y33_N1 B4 B4
Column I/O 312 LVDS32n/DEV_OE 304 2 IOC_X2_Y33_N0 B3 B3
Column I/O 313 LVDS32p/DEV_CLRn 304 2 IOC_X2_Y33_N1 C4 C4


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