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The EP1C3, a member of the Cyclone^™ device family, provides 3,210 registers; 59,904 memory bits; and 2,910 logic elements. The Cyclone device meets the low-voltage requirements of 1.8-V applications and supports multiple I/O standards including LVDS, LVTTL, LVCMOS, PCI, SSTL-3 Class I & II, and SSTL-2 Class I & II.

The EP1C3 is available in 100-pin TQFP packages with 61 I/O pins and 144-pin TQFP packages with 100 I/O pins. The device has 2,910 logic elements grouped into 291 LABs. These LABs are arranged into 13 rows and 24 columns. The embedded memory consists of one column of M4K memory blocks, containing a total of 59,904 RAM bits. Each M4K block can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM, ROM, FIFO buffers, and shift registers.

Each I/O element contains a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. The I/O element contains individual input, output, and output enable registers. The input register provides fast setup times, the output register provides fast clock-to-output times, and the output enable register provides fast clock-to-output enable times. The EP1C3 also contains four dedicated clock pins and eight dual-purpose clock pins for large fan-out control signals. In addition, the EP1C3 contains one phase-locked loop (PLL), which provides general purpose clocking with clock multiplication and phase shifting as well as high-speed output for high-speed differential I/O support.

The EP1C3 also supports ICR and JTAG BST. The EP1C3 JTAG Instruction Register length is 10; the Boundary-Scan Register length is 113; and the JTAG ID code is 0x020810DD.

Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to the current Quartus® II Software Release Notes, available on the Altera® web site. For complete information on the EP1C3 device, refer to the current Cyclone Programmable Logic Device Family Data Sheet, which is available from the Literature section of the Altera web site.

The following table displays the pin-out information for EP1C3 devices:

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