See Also

Based on flash memory technology, the EPCS1 configuration device is a reprogrammable serial memory device that stores configuration data for all SRAM-based Altera^® devices supported by the Quartus^® II software. In SRAM-based devices such as Cyclone^™ devices, the configuration data must be reloaded whenever the system initializes, or whenever you want new configuration data. A single EPCS1 device has a capacity of 1 Mbit of data. You can use the Nios^® embedded processor, SOPC Builder, and the active serial memory interface block to store and retrieve data or configuration files from any memory location within the EPCS1 device.

The Quartus II software can generate Programmer Object Files (.pof) that you can use to program configuration devices, such as EPCS1 devices. The Quartus II software can combine SRAM Object Files (.sof) for multiple Cyclone devices into a single EPCS1 device. When programming a chain of devices with an EPCS1 device, the first device in the chain must be a Cyclone device.

Preliminary support for new device packages may be available for this device. Pin-outs for devices with preliminary support are subject to change. For information on preliminary device support, refer to Quartus II Software Release Notes, available on the Altera web site. The EPCS1 configuration devices are available in 8-pin SOIC packages. For complete information on the EPCS1, refer to the current Serial Configuration Devices Data Sheet, which is available from the Literature section of the Altera web site.

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