Directs the Quartus^® II software to unmap WYSIWYG primitives during synthesis. When this option is turned on, the Quartus II software unmaps the logic elements in an atom netlist to gates and remaps the gates back to Altera^® LCELL primitives, using the technology mapper you specified with the Technology Mapper logic option in the Default Logic Option Settings page of the Settings dialog box (Assignments menu).

This option does not create registers, but may reduce the number of registers in the design. Also, node names can change when this option is turned on.

This option is not available if Quartus II Integrated Synthesis is being used. In addition, you can set the Never Allow setting in the Netlist Optimizations logic option for nodes or entities so that the Quartus II software does not unmap certain logic elements in the current design.

Directs the Quartus II software to perform gate-level register retiming during synthesis. This option allows registers to be moved across combinatorial logic to balance timing, but does not change the functionality of the current design. This option moves registers only across combinatorial gates, and not across user-instantiated logic cells, memory blocks, DSP blocks, or carry or cascade chains. Carry or cascade chains are always left intact during register retiming.

One of the more powerful features of register retiming is the ability to move registers from the inputs of a combinatorial logic block to the block's output, potentially combining the registers. In this case, some registers are removed and one register is created at the output. Registers can be moved and combined in this manner only if the following conditions are met:

• All registers have the same clock signal.

• All registers have the same clock enable signal.

• All registers have asynchronous control signals that are active under the same conditions.

• At the most, only one register has an asynchronous load signal other than VCC or GND.

It is also possible to create multiple registers at the input of a combinatorial logic clock from a register at the output of a combinatorial logic block. In this case, the new registers have the same clock and clock enable signals. The asynchronous control signals remain the same or are derived to provide equivalent functionality.

Node names for primitives can change when this option is turned on. Primitive node names are specified during synthesis and are in the atom netlist; therefore, when this option is turned on, node names may change as primitives are removed and created. The node name changes may cause problems if you are using a LogicLock^™ region or verification flow that requires fixed node names.

When you use this option for a design, the Quartus II software may not be able to honor certain synthesis directives or pragmas, such as syn_preserve or syn_keep, that you used in your original design because the EDA tool you used for the design did not include the synthesis directives or pragmas in the Verilog Quartus® Mapping File (.vqm) or EDIF netlist file it generated for the design. To accomplish the functionality that the synthesis directives or pragmas would have provided, you may need to use the Netlist Optimizations logic option to specify that the Quartus II software not move certain registers in the current design during register retiming.

The Quartus II software never moves the following registers during register retiming:

• Registers that have any timing requirements other than f_MAX, t_CO, or t_SU.
• Registers that feed asynchronous control signals on another register.
• Registers that feed the clock of another register.
• Registers that feed or are fed by a register in another clock domain.
• Registers that directly feed or are fed by a pin.

In addition, you can set the Never Allow setting in the Netlist Optimizations logic option for nodes or entities so that the Quartus II software does not move certain registers in the current design during register retiming.

The Gate-Level Retiming section of the Compilation Report window list the registers that were removed and created during register retiming.

Directs the Quartus II software to move logic across registers that are associated with I/O pins during register retiming to trade off t_CO and t_SU with f_MAX. When you turn on this option, register retiming can affect registers that feed and are fed by I/O pins. If you do not turn on this option, register retiming does not touch any registers that are connected to I/O pins.

When you turn off Perform gate-level register retiming, this option is dimmed to indicate that it is not available. When you turn on Perform gate-level register retiming, this option is turned on by default. In addition, you can set the Never Allow setting in the Netlist Optimizations logic option for nodes or entities so that the Quartus II software does not move certain blocks of logic across registers in the current design during register retiming.

Directs the Quartus II software to use timing information from the Fitter to optimize netlists during synthesis. When you turn on this option, the Quartus II software performs a first pass through synthesis, where it uses the Fitter to compute timing delays in the design's netlist during an estimated fit, and then uses the timing delays to identify the design's critical path, that is, the portions of the netlist that are critical for performance. The Quartus II software then performs a second pass through synthesis, where it improves the critical path using more performance–oriented synthesis and improves logic cell usage on the portions of the netlist that are less critical for performance.

Node names for primitives can change when this option is turned on. Primitive node names are specified during synthesis and are in the atom netlist; therefore, when this option is turned on, node names may change as primitives are removed and created. The node name changes may cause problems if you are using a LogicLock region or verification flow that requires fixed node names.

Although this option reduces area and improves performance in many designs, the option does not produce the same results in all designs because of the individual characteristics of each design; this option may even increase area and decrease performance in certain designs. Also, because it requires that the Quartus II software use the Fitter to establish timing information for synthesis, this option may require up to a 50% longer compilation time than compilations that do not include this option.

You can set the Never Allow setting in the Netlist Optimizations logic option for nodes or entities so that the Quartus II software does not use fitter timing information to optimize the netlist for the nodes or entities.

The Resource Utilization by Entity - Second Pass section of the Compilation Report window lists the new utilization of logic elements after the second pass through synthesis.

When you use the SignalTap^® II incremental routing feature, this option is dimmed to indicate that it is not available.

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