A feature that allows you to analyze internal device nodes at the system speed without affecting the existing placement and routing in a design. SignalTap^® II incremental routing shortens the debug process by allowing you to analyze post-compilation nodes without requiring a full recompile. This feature is available for only APEX^™ II, APEX^™ 20K, ARM^®-based Excalibur^™, Cyclone^™, Stratix^™, and Stratix^™ GX devices.

Before using the SignalTap II incremental routing feature, you must perform a smart compilation by turning on Automatically turn on smart compilation if conditions exist in which SignalTap II with incremental routing is used, in the SignalTap II Logic Analyzer page of the Settings dialog box (Assignments menu). Also, you must reserve trigger or data nodes for SignalTap II incremental routing using the Trigger Nodes allocated and Data Nodes allocated boxes before compiling the design, and you must assign a SignalTap II incremental routing source by selecting SignalTap II: post-fitting in the Filter list in the Node Finder.

Back to Top