Netlist Optimizations logic option Description

Netlist Optimizations logic option

A logic option that specifies whether the Compiler should perform advanced netlist optimizations on the specified node or entity.

You can choose one of the following settings:

Always Allow Allows the Compiler to alter the node or entity, even if doing so affects the timing or performance of the design. Altera^® does not recommend using this setting.

Never Allow Prevents the Compiler from altering the node or entity.

Default Allows the Compiler to duplicate, move, or change the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not affect the timing or performance of the design.

This option is useful for preserving I/O timing on specific pins and registers in a design where you want to perform netlist optimization. This option is also useful for preserving the synthesis of a specific node or entity, for example, preserving the name of a register.

This option is ignored for gate-level retiming if it is applied to anything other than a register or a design entity containing registers; for synthesis and fitting, this option is ignored if it is applied to anything other than a logic cell or design entity. This option is available for APEX^™ 20K, APEX 20KC, APEX 20KE, APEX^™ II, ARM^®-based Excalibur^™, Cyclone^™, Stratix^™, and Stratix^™ GX devices.

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Always Allow	Allows the Compiler to alter the node or entity, even if doing so affects the timing or performance of the design. Altera^® does not recommend using this setting.
Never Allow	Prevents the Compiler from altering the node or entity.
Default	Allows the Compiler to duplicate, move, or change the synthesis of the node or entity, or allows register retiming during netlist optimization, only if doing so does not affect the timing or performance of the design.