Name & Setting

Allows you to select an assignment name and setting for the specified entities.

Name	Setting
Allow XOR Gate Usage	On\|Off
Auto Carry Chains	On\|Off
Auto Cascade Chains	On\|Off
Auto DSP Block Replacement	On\|Off
Auto Global Clock	On\|Off
Auto Global Memory Control Signals	On\|Off
Auto Global Output Enable	On\|Off
Auto Global Register Control Signals	On\|Off
Auto Implement in ROM	On\|Off
Auto Logic Cell Insertion	On\|Off
Auto Open-Drain Pins	On\|Off
Auto Packed Registers	Off\|Normal\|Minimize Area\|Minimize Area with Chains
Auto Parallel Expanders	On\|Off
Auto RAM Replacement	On\|Off
Auto Shift Register Replacement	On\|Off
Auto Turbo Bit^™	On\|Off\|Auto
Carry Chain Length	*<length>*
Cascade Chain Length	*<length>*
Logic Cell Insertion - I/Os Fed by Carry or Cascade Chains	On\|Off
Logic Cell Insertion - Individual Logic Cells	On\|Off
LogicLock^™ Import File Name	*<file name>*
Optimization Technique	Area\|Speed
Parallel Expander Chain Length	*<length>*
Preserve Hierarchical Boundary	Off\|Firm\|Relaxed
Remove Duplicate Logic	On\|Off
Technology Mapper	Auto\|LUT\|Product Term\|ROM

See the Description field for a description of parameter assignments.

- PLDWorld -

Created by chm2web html help conversion utility.