A logic option that determines how strictly the hierarchical boundaries between design entities should be maintained during logic synthesis.
You can choose one of the following settings:
| Off | Completely ignores boundaries and therefore allows unlimited optimization. This setting provides the greatest logic minimization. |
| Relaxed | Allows only partial cross-boundary optimization, which may reduce the compilation time. Non-trivial inputs and outputs of the entity are visible during simulation and timing analysis. |
| Firm | Strictly maintains hierarchical boundaries. This setting may increase compilation time, increase logic cell count, and negatively affect design performance. |
This option applies only to the design entity to which it is assigned; lower-level entities do not inherit their parent entity's setting for this option. This option is available for all Altera® devices supported by the Quartus® II software.
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