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Lists information about the input pins for the device.
Information is provided as follows:
| Heading | Description | Value |
|---|---|---|
| Name | Shows the name of the pin. | <pin name> |
| Pin # | Shows the pin number. | <pin number> |
| Migration Pin # | Shows the pin number of the largest compatible migration device. This column appears only if you select an ACEX® 1K, FLEX 10KE, or MAX® 7000 device for compilation and turn on Base the Pin-Out File (.pin) and floorplan package views on the largest selected SameFrame™ device in the Migration Devices dialog box, which is available from the Device page of the Settings dialog box (Assignments menu). |
<migration pin number> |
| X coordinate | Shows the X coordinate location of the input pin. This column appears only if you specify a Cyclone™, Stratix™, or Stratix™ GXdevice for compilation. |
<X coordinate> |
| Y coordinate | Shows the Y coordinate location of the input pin. This column appears only if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
<Y coordinate> |
| Cell number | Shows the cell number that corresponds to the input pin. This column appears only if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
<cell number> |
| MegaLAB™ Row |
Shows the MegaLAB row number to which the pin is assigned. This column only appers if you specify an APEX™ 20K, APEX 20KC, APEX 20KE, APEX™ II, or ARM®-based Excalibur™ device for compilation. |
<MegaLAB row number> |
| MegaLAB Col. |
Shows the MegaLAB column number to which the pin is assigned. This column appears only if you specify an APEX 20K, APEX 20KC, APEX 20KE, APEX II, or ARM-based Excalibur device for compilation. |
<MegaLAB column number> |
| LAB |
Shows the LAB number to which the pin is assigned. This column appears only if you specify a MAX 3000 or MAX 7000 device for compilation. |
<LAB number> |
| Combinational Fan-Out | Shows the number of fan-out to combinatorial logic for the input pin. This column appears only if you specify a Cyclone, MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
<number of fan-out> |
| Registered Fan-Out | Shows the number of fan-out to registered logic for the input pin. This column appears only if you specify a MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
<number of fan-out> |
Row |
Shows the row to which the pin is assigned. This column appears only if you specify an ACEX 1K or FLEX 10KE device for compilation. |
<row number> |
| Col. | Shows the column number to which the pin is assigned. | <column number> |
| Fan-out | Shows the fan-out for the pin. | <fan-out number> |
| Global | Shows whether the pin is a global source. | yes | no |
| I/O Register | Shows whether the pin uses an I/O register to register either an input or output signal. This column does not appear if you specify an APEX II, a MAX 3000, or MAX 7000 device for compilation. |
yes | no |
| Input Register | Shows whether the pin uses an input register to register an input signal. This column appears only if you specify an APEX II, MAX 7000AE, or MAX 7000B device for compilation. |
yes | no |
| Use Local Routing Input | Shows whether the pin uses a local routing resource to route into the adjacent LAB. This column does not appear if you specify a Cyclone, Stratix, or Stratix GX device for compilation. |
yes | no |
| Power Up High | If a peripheral register exists, shows whether the pin powers up high or low. This column does not appear if you specify a MAX 3000 device for compilation. |
yes | no |
| Delay Chain | Shows whether the pin uses an input delay chain. This column does not appear if you specify a MAX 3000 or MAX 7000AE device for compilation. |
yes | no |
| PCI I/O Enabled | Shows whether the PCI I/O logic option is applied to the pin. The PCI clamp diode is turned on automatically when you turn on this option. This column does not appear if you specify a MAX 3000 or MAX 7000 device for compilation. |
yes | no |
| Single-Pin CE | Shows whether the clock enable signal is driven from the local interconnect. This column does not appear if you specify a Cyclone, MAX 3000, MAX 7000, Stratix, or Stratix GX device for compilation. |
yes | no |
| FastRow™ Interconnect | Shows whether the pin drives a row interconnect line that connects FastRow interconnect lines. This column appears only if you specify an APEX 20K, APEX 20KC, APEX 20KE, APEX II, or ARM-based Excalibur device for compilation. |
yes | no |
| Bus Hold |
Shows whether the Enable Bus-Hold Circuitry logic option is applied to the pin. This column appears only if you specify an APEX II, Cyclone, MAX 7000B, Mercury™, Stratix, or Stratix GX device for compilation. |
yes | no |
| Weak Pull Up | Shows whether the Weak Pull-Up Resistor logic option is applied to the pin. This column appears only if you specify an APEX II, Cyclone, MAX 7000B, Mercury, Stratix, or Stratix GX device for compilation. |
On | Off |
| I/O Standard |
Shows the I/O standard assigned to the pin. This column does not appear if you specify a FLEX® 6000 device for compilation. |
1.5-V | 1.8-V | 2.5-V | 3.3-V PCI | 3.3-V PCI-X | 3.3-V PCML | AGP 1x | AGP 2x | Compact PCI | CTT | Differential HSTL | Differential SSTL-2 | GTL GTL+ | HSTL Class I, II | HSTL Class III, IV | HyperTransport™ | LVCMOS | LVDS | LVPECL | LVTTL | SSTL-2 Class I, II | SSTL-3 Class I, II | SSTL-18 Class I, II | TTL |
| Termination | Shows whether the Termination logic option is applied to the input pin. This column appears only if you specify a Cyclone, Mercury, Stratix, or Stratix GX device for compilation. |
On | Off |
The following example shows a portion of the Input Pins section generated for a sample design:
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