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You can create or modify design files that contain custom megafunction variations of Altera-provided functions. You can then instantiate the custom megafunction variations in a design file for use with the FPGA Express or FPGA Compiler II and Quartus^® II software. This procedure shows only how to instantiate a RAM megafunction using Verilog HDL; however, you can use similar procedures to instantiate other Altera-provided functions.

1. If you have not already done so, proceed to Set Up the FPGA Express Working Environment or Set Up the FPGA Compiler II Working Environment.

2. If you have not already done so, create a Verilog HDL design in the FPGA Express software, or in the FPGA Compiler II software, by using one of the following procedures:

• Create a Design for Use with the FPGA Express Software
• Create a Design for Use with the FPGA Compiler II Software
3. Open the MegaWizard^® Plug-In Manager (Tools menu) and specify appropriate options for the megafunction you want to instantiate.

The MegaWizard Plug-In Manager generates custom megafunction variations that are based on Altera-provided megafunctions, including library of parameterized modules (LPM) functions, as well as Altera^® megafunctions.

Refer to the following example to create a Verilog HDL custom megafunction variation of the lpm_ram_dq function:

• Example of Creating a Verilog HDL Custom Variation of the lpm_ram_dq Function

4. To prepare the Verilog  HDL design for synthesis with the FPGA Express or FPGA Compiler II software, you must specify that the tool should treat the design file created in the MegaWizard Plug-In Manager as a "black box." The software then makes the correct connections to the ports in the EDIF netlist file (.edf). The Quartus II software reads in the EDIF netlist file as an EDIF Input File (.edf) and processes the instantiated megafunction. If the top-level design file doesn't have a module declaration, the FPGA Express or FPGA Compiler II software infers a "black box". The MegaWizard Plug-In Manager also generates a file with the extension _bb.v that can be used as an empty module declaration for use as a black box. To treat the design file for the megafunction as a "black box," refer to the following example:

• Example of Creating a "Black Box" for a Verilog HDL Custom Megafunction Variation Using the FPGA Express or FPGA Compiler II Software

The design file generated by the MegaWizard Plug-In Manager must be in the same directory as the EDIF Input File or added to the Quartus II project.

5. If necessary, perform a functional simulation of the design using the VCS software or another simulation tool.

6. Continue to Generate EDIF Netlist Files with the FPGA Express Software, or Generate EDIF Netlist Files with the FPGA Compiler II Software.

7. If you have not already done so, create a new project or open an existing project.

8. Compile the design in the Quartus II software.

9. If necessary, proceed to Perform a Timing Simulation with the ModelSim^® Software or simulate the design with another Verilog HDL simulation tool.




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