See Also

To specify that the FPGA Express or FPGA Compiler II software should treat the use_lpm_ram_dq.v file that you created in Example of Creating a Verilog HDL Custom Variation of the lpm_ram_dq Function as a "black box," refer to the following code sample from the top-level design file. In this example, the top-level design file is verilog_design.v. To modify the source code for the verilog_design.v file to define the module name and port type and to specify that the module is a black box, you can use the use_lpm_ram_dq_bb.v empty module declaration and add it to the verilog_design.v top-level design file as shown in the following code sample:

module verilog_design 	(
			address,
			clock,
			wen,
			data,
			q
			);
			
input  [7..0]		address;
input			clock;
			wen;
input  [7..0]		data;
output [7..0]		q;

// direct instantiation of the "wrapper"
use_lpm_ram_dq u1	(
			.address	(address),
			.inclock	(clock),
			.we	(wen),
			.data	(data),
			.q	(q)
			);
endmodule

// empty module for port direction information
module use_lpm_ram_dq (
	address,
	we,
	inclock,
	outclock,
	data,
	q);

	input	[7:0]  address;
	input	  we;
	input	  inclock;
	input	  outclock;
	input	[7:0]  data;
	output	[7:0]  q;

endmodule

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