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To generate an EDIF netlist file with the FPGA Express software for use with the Quartus^® II software:

1. If you have not already done so, perform 4. Assign Design Constraints and Optimize Design with the FPGA Express^® Software.

2. To generate Quartus II–compatible EDIF netlist files, select the optimized design implementation and click the Export Netlist button on the toolbar. In the Export Netlist dialog box, specify the following options:

   1. In the Export Directory box, specify the name and location of the directory for the EDIF netlist files.

   2. Under Place and Route, select the EDIF netlist file's output bus in the Bus Style list. The Quartus II software accepts either flattened or unflattened buses. In the FPGA Express software, the default setting, EXPAND, flattens each bus by writing each bus bit as an individual I/O port. To export an EDIF netlist file without flattening the bus names, select any of the other settings, which include delimiters for different bus notations:[], <>, (), and {}.

      If you are using a custom megafunction variation for content-addressable memory (CAM), ClockLock® PLL, LVDS, or RAM functions generated by the MegaWizard® Plug-In Manager, you must select %s{%d:%d} in the Bus Style list.

   3. If you wish to generate a VHDL or Verilog HDL netlist file for functional simulation prior to Quartus II compilation, select a language option (VHDL or Verilog) from the Output Format list. Otherwise, NONE is selected by default.

   4. To close the Export Netlist dialog box, click OK. The FPGA Express software creates the following Quartus II–compatible files:
      • <design name>.edf (EDIF format)
      • <design name>.tcl, a Tcl Script File (.tcl) that contains a Tcl script for compiling the design with the Quartus II software
      • <design name>.lmf, a Library Mapping File (.lmf) that maps FPGA Express functions to Quartus II functions

3. Copy all the output files to a Quartus II project directory. Process the <design name>.edf file with the Quartus II Compiler.

   You must specify the FPGA Express generated <design name>.lmf as the LMF for the project when specifying the EDA tool input settings.

4. To continue with the FPGA Express design flow, proceed to 6. Analyze Design Results with the FPGA Express Software.

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