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You can use the Synopsys^® FPGA Express Time Tracker static timing analyzer to display estimated delays of critical paths in your project. This Time Tracker provides timing information and a detailed listing of critical paths.

To use the Time Tracker timing analyzer:

1. If you have not already done so, perform 4. Assign Design Constraints and Optimize Design with the FPGA Express^® Software and 5. Generate EDIF Input Files with the FPGA Express Software.

2. Select the design implementation icon in the Chips window and choose View Results (right button pop-up menu) to display the Time Tracker tabs.

3. Analyze the timing of your design by viewing the different tables within the Clocks, Paths, and Ports Time Tracker tabs:

   • To analyze the clock frequency (f_MAX), click the Clocks tab. The table in the Clocks tab contains a column showing the actual clock frequency for each clock in your design next to the desired frequency derived from your timing constraints. Clocks that fail to meet their constraints are highlighted in red.

   • To check critical timing paths, click the Paths tab. The table in the Paths tab contains an Est. Delay column displaying path delays. Paths that fail to meet constraints are highlighted in red. You can select a path or path group to display additional tables with increasing detail, in order to identify exactly which paths failed to meet their timing constraints.

   • To view I/O port delays, click the Ports tab. The Ports tab displays the slack for each I/O port, for example, the clock period minus the propagation delay through the port in the Input Slack column for input ports and the Output Slack column for output ports. Negative values are highlighted in red, indicating that the propagation delay exceeds the clock period, causing a timing violation.

4. If necessary, change the design logic or adjust your timing constraints, and re-optimize the design.

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